Frequency low by factor 9
Hi,
I used a Nucleo-F303RE board as template for my own hardware. Timers and clockfrequency are running fine on the NUCLEO but they are slow by factor 9 on my own hardware. USARTs are running on the exspected baudrate. Factor 9 gives a hint to the PLL block in clock generation. I recently learned that PLL is running on VDDA. I blocked VDDA from VDD with a bead.
Is it the PLL?
Why does it not lock, where can I check?
Poor VDD? Poor blocking VDDA from VDD?
Poor XTAL? Something totally different.
Why the correct baudrate?
THX for hints.
Cheers Detlef
