From H7-series to U5-series - problem with OCTOSPI

[Southbranch]

Hi,

I have two custom boards using the same OCTOSPI HyperFlash and for some reason the memory fails to run at higher speeds with U5-board.

Board 1
-H7 MCU at 550 MHz
-OCTOSPI at 160 MHz works fine! (max clk is 166 MHz)

Board 2
-H5 MCU at 160 MHz
-OCTOSPI at 160 MHz fails in W/R.... (works fine up to 110 MHz)

Could there be any specific reasons why the U5 cannot handle the OCTOSPI running at 160 MHz, which in this case is the same speed as the MCU clock?

[Tesla DeLorean]

Check pin drivers / SPEEDR. Check if the memory has lower drive levels

[Southbranch]

Could you please elaborate what you mean with SPEEDR and drive levels?

I have checked voltage pins and they are fine. Also checked clock and other signals, a bit of ringing on both boards but accept that, it seems ok. However, my scope only measures up to 100 MHz and thus I really cant say for sure how it looks like at 160 MHz.

Board 1 is a 6-layer PCB setup and Board 2 is a 4-layer. I have checked trace impedance to be around 50 ohms on both boards.

 

[KDJEM.1]

Hello @Southbranch , 

Could you please refer to STM32U5 data sheet and check the maximum OCTOSPI clock frequency in table OCTOSPI characteristics in DTR mode (with DQS)/HyperBus(1)(2) 

The below table is OCTOSPI characteristics in DTR mode (with DQS)/HyperBus for STM32U5A.

 

Thank you.

Kaouthar

 

[Southbranch]

Thank Kaouthar,

However I am a bit confused, I am using the Hyperbus OCTOSPI in memory mapped mode and in AN5050 I just found this table saying the U5-series should support 160 MHz.

Please help me clarify,

many thanks in advance

[KDJEM.1]

Hi @Southbranch ,

 

The max AHB bus frequency access indicated in An5050 table 2 is the maximum bus frequency used for the data register.

You can show the max OCTOSPI communication frequency in "Max OCTOSPI speed (MHz) line" in AN5050 table 2.

 

Note that this max frequency depends on voltage scaling as mentioned in the datasheet.

I hope this answer your request.

Thank you.

Kaouthar 

[Southbranch]

Thanks,

I am using 3.3V + single clock + memory mapped mode.

I seems 160 MHz should be supported, but I am still confused since you yellow marked double rows in the tablle.

Could you please explicity confirm?

[Tesla DeLorean]

Well typically they run the PERIPHERAL 2X faster to accommodate the data side rate of DDR / DTR, the peripheral side clock being 160 MHz, the memory side clock being 80 MHz, and the data latching on both edges.

The SPEEDR setting (GPIO_InitStruct.Speed) for the GPIO determines how aggressively the pin is driven, it's basically a SLEW RATE under another name, but determines the amount of energy imparted by the pin-driver transistor chain, for SHORT traces presenting LOW LOADS one can back-off the "speed" so the lines don't ring.

The pin drivers for the H7 and U5/H5 are not identical. Most ST parts top out at around 100-110 MHz at the pin level, for most practical purposes.

[Southbranch]

Ok, thank you both