FSM data bus during read transactions

[Brickman]

Hi

I'm testing a FMC connection between the mcu on a STM32H753I-EVAL2 board, and a FPGA acting as a SRAM device.

Write operations looks OK, but when I try to perform a read operation, it looks like that even thought the nxe and noe behave as expected, the mcu is driving the data bus with random data, not allowing the FPGA to drive desired data.

I tried various timing settings, and also changed to PSRAM, in regular and muxed mode, but nothing changed.

I also turned on the MPU, with a allow all transactions setting.

 

Can you please point me to what I'm missing here?

[waclawek.jan]

Aren't there some other memories on the EVAL board connected to FMC? Can't they be those driving the data bus?

JW

[Brickman]

Thank you!

You were absolutely correct, the flash memory was connected to the same nxe, after removing the serial short resistor, everything started to work well.

 

Ron