This will not work with your settings:
- You have set the divider for PLLM to /16, which results in only 1.5MHz at 24MHz. However, CubeMX points out that PLLM must be between 2.66-16MHz.
- You have set the factor for PLL *N to x8, which results in 12MHz for you, but must be between 96-344MHz.
- You have set the divider PLL /Q to /6, which would generate your desired 2MHz (that you think you have to create) from 12MHz, but here too CubeMX points out that PLLQ must be between 8-170MHz. However, the generated SAI frequency is not the one that is output at the clock pin, but the one that clocks as sai_x_ker_ck the SAI block.
If you solve the clock configuration problem in STM32CubeMX, this results in a PLLQ of 24MHz (PLLM=/2, PLLQ=x8/4), which you can easily divide to 2MHz with the MCKDIV contained in the SAI (RM0440, section 40.4.8). Your IOC contains a value of 11 for MCKDIV, which you only need to set to 12 at mentioned 24MHz.
You should also take the opportunity to upgrade to the new version of STM32CubeMX.
Regards
/Peter