GPDMA Linked List in Secure code on STM32N6

[ERROR]

Hi,

The example for FSBL works as described

https://community.st.com/t5/stm32-mcus/how-to-configure-the-linked-list-mode-in-stm32cubemx/ta-p/693779

But if the same approach is applied to Appli (Secure) code, the "User Setting Error" raised in DMA IRQ.

I use the XIP configuration.

Could you please elaborate chages to be made in Secure code?

 

[ERROR]

Looks like I am not alone with this

https://community.st.com/t5/stm32-mcus-embedded-software/re-hpdma-linked-list-mode-user-setting-error-nucleo-n6/m-p/788474

[ERROR]

BTW, I played with MPU regions, and even disabled the MPU at all. It had no effect.

[neil1106]

I am having the same issue with "User Setting Error" on GPDMA.

Edit: I found the root of my issue. I based my code off the example ADC_SingleConversion_TriggerTimer_DMA for the NUCLEO-N657X0-Q, instead of FSBL I used secure application. So if anyone else sees the same error this is the cause.

The problem is in two places.

1. When using a secure application in addition to the FSBL there is a new method added to main.c called SystemIsolation_Config. Here the RIF aware config is set for the GPDMA again.

 if (HAL_DMA_ConfigChannelAttributes(&handle_GPDMA1_Channel0,DMA_CHANNEL_SEC|DMA_CHANNEL_NPRIV)!= HAL_OK )
 {
 Error_Handler();
 }

if you attach any peripheral (such as ADC) to the GPDMA in the application context you will see another call to this method in stm32n6xx_hal_msp.c  HAL_ADC_MspInit

if (HAL_DMA_ConfigChannelAttributes(&handle_GPDMA1_Channel0, DMA_CHANNEL_PRIV|DMA_CHANNEL_SEC
 |DMA_CHANNEL_SRC_SEC|DMA_CHANNEL_DEST_SEC) != HAL_OK)
 {
 Error_Handler();
 }​

it gets called before the SystemIsolation_Config one. Commenting out the second one here fixes the first issue.

• The second issue is that the DMA buffer needs to be in an uncacheable area of memory. Disabling either the Dcache or explicitly placing the buffer in memory marked as uncacheable allows the DMA to work. The code in the example method MPU_Config 

default_config.BaseAddress = __NON_CACHEABLE_SECTION_BEGIN;
 default_config.LimitAddress = __NON_CACHEABLE_SECTION_END;

does not work in the application context. The base and limit address is the same so if you use the __NON_CACHEABLE macros they do nothing. All you will see is zeroes at the memory addresses and the DMA user error. Changing the limit address to base address + your required buffer size allows the DMA to work.

 

[ERROR]

Hi @neil1106 

Thank you for your efforts!

The bullet #1 is exact.

 

Regarding item #2, the DMA buffer can reside in any memory region accessible by the DMA controller; however, cache clean or invalidate operations must be performed, depending on whether the CPU writes to or reads from that memory.

[IO1]

The reason 

default_config.BaseAddress = __NON_CACHEABLE_SECTION_BEGIN;
 default_config.LimitAddress = __NON_CACHEABLE_SECTION_END;

does not work is the wrong definition of .noncacheable section in the linker file.

It should be the same as in FSBL project.

.noncacheable :

{

. = ALIGN(8);

__snoncacheable = .;/* create symbol for start of section */

KEEP(*(.noncacheable))

. = ALIGN(8);

__enoncacheable = .; /* create symbol for end of section */

} > RAM