GPIO connections of OCTOSPI on external flash and ram

[blanc6389]

My MCU is the STM32H723. To save GPIO pins, I would like to use the following architecture:
- Connect external HyperRAM and Flash to one OCTOSPI bus. 
- Use multiplexed mode to access OCTOSPIM_P1 and OCTOSPIM_P2.
- Map external RAM and Flash to different addresses by memory mapped mode

Based on the information from [this STMicroelectronics application note](https://www.st.com/resource/en/application_note/an5050-getting-started-with-octospi-hexadecaspi-and-xspi-interface-on-stm32-mcus-stmicroelectronics.pdf), it seems possible. Is that correct?

Another question: After the memory mapped mode is enabled, the external Flash is read-only, but the external RAM is still readable and writable. Is that correct?

[LCE]

It seems possible, but I wouldn't do it:

This will be hard for PCB layout, especially if you must meet EMC requirements.

And then your "memory-mapped mode" still has to switch the correct CS = chip select signal, I don't know if there is an automatism at the OSPI peripheral for that.

[KDJEM.1]

Hello @blanc6389 and welcome to the community,

 

With Multiplexed mode enabled: Both memories are connected to an OCTOSPI I/O manager port. Only the second memory requires an additional GPIO for NCS from the remaining OCTOSPI I/O manager port. It requires up to 13 GPIOs as shown in the below figure.

This feature allows two external memories to be exploited using few pins on small packages, in order to reduce the number of pins, PCB design cost and time.

In Multiplexed mode, OCTOSPI1_NCS and OCTOSPI2_NCS work in the same way, then in Non-multiplexed mode they have to be assigned to their respective OCTOSPIM_Pn_NCS.

Please also respect the minimum number of cycles needed to switch from an OCTOSPI to another can be configured.

May 26.4.3 OCTOSPIM multiplexed mode section in RM0468 can help you.

 

Thank you.

Kaouthar