H7 power dissipation and lifetime, how to manage?

[regjoe]

Hello,

I came across this document here https://www.st.com/resource/en/application_note/dm00622045-stm32h7-series-lifetime-estimates-stmicroelectronics.pdf

We have a H75x custom board running the MCU in VOS1 at 400MHz with external 1.2V core power supply.

According to this description here

According to Figure 2, when VOS1, VDD = 3.3 V, VCORE = 1.2 V and operation ratio of 100%. Some examples are
illustrated such as:
• Tj = 105°C the lifetime estimation is > 10 years
• Tj = 125°C the lifetime estimation is 4 years
• Tj = 140°C the lifetime estimation is 2 years
In the same conditions and for an operation ratio of 20%, the lifetime estimation is as following:
• Tj = 125°C the lifetime estimation is 20 years
• Tj = 140°C the lifetime estimation is 10 years

the power consumption, heat dissipation and lifetime is influenced by "operation ratio". What does operation ratio mean and how can I influence/control it? Does this mean that only a part of chip silicon is powered/used? Or time spent in the idle loop, assuming the MCU is running in lowest VOS mode and/or clock frequency during idle time?

Thanks,

Jochen

 

 

 

 

 

 

[Andrew Neil]

So this:

 

https://www.st.com/resource/en/application_note/dm00622045-stm32h7-series-lifetime-estimates-stmicroelectronics.pdf#page=4

 

Indeed, the term "operation ratio" is vague and needs proper definition.

 

I guess it's some sort of "duty cycle": presumably, the 20% indicates the proportion of time operating at the high junction temperature - but what is happening in the other 80% of the time?

Presumably it would also depend on how long the high temperature is maintained?

 

[regjoe]

I tend to agree with you. After all, this is one of those documents that create more questions than give answers... :)

I wonder what happens to the chip if lifetime is over? MCU clock stutters (but nobody cares about), flash bits are worn out, chip goes up in flames, ...?

So the primary goal in order to save lifetime is to keep the junction temperature below 125°C?

This can be acchieved via power consumption reduction and chip cooling. Latter is hard to do.

Power consumption is proportional to MCU core voltage, clock frequency, active silicon, ...

But is switching VOS levels, frequency and turning on/off temporarily unused peripherals really a practical way to go in an industrial application? I guess most applications nowadays are still running a super loop at VOS0. What happens? Never heard about failing systems due to running at CPU maximum clock speed. Is this only STM business?  

 

 

 

[Ozone]

> But is switching VOS levels, frequency and turning on/off temporarily unused peripherals really a practical way to go in an industrial application?

Very few industrial applications have an estimated lifespan of 10 years, technological obsolescence usually hits earlier.

Automotive applications are different, they often require qualification at much higher ambient temperatures. And you would need to add about 10 to 30°C between Ta and Tj.

> Is this only STM business?  

Certainly not.

[Ozone]

> What does operation ratio mean and how can I influence/control it?

I would expect this term to mean the relative time of the system operating at given temperature.
Higher temperatures and higher currents cause electromigration (migration of n-/p- doping atoms), which degrades the die structures over time.
Mind you, these are all statistical measures.
And second, the key temperature here is Tj, not Ta.

[LCE]

> This is the first time I ever heard about limited uC lifetime.
> This made me wonder if newer ST uCs are less reliable if running at nominal CPU speed.

Same here! :D

> Second I try to measure the CPU load... 

And I wonder if that is the only problem - how much does it "help" for longevity if the CPU sleeps, but DMA & peripherals are running in parallel ? Even though these usually run at 1/2 SysClock.

RTOS: I'm sure these have some "sleep" states ?

Measurement: the M7 ARM has the very accurate cylce counter "CYCCNT", incrementing with each CPU clock cycle, which is probably the most accurate internal tool for timing measurements.

I use it together with a 1 ms SysTick.

/* +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ */
/* CPU cycle count activation for debugging */
	CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
	DWT->LAR = 0xC5ACCE55;
	DWT->CYCCNT = 0;
	DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk;
	DWT->CTRL |= DWT_CTRL_PCSAMPLENA_Msk;

/* for accurate measurements, disable IRQs 
 * and use memory barriers */
__DSB();
__disable_irq();

	u32CycStart = DWT->CYCCNT;

source code to be tested

	__DMB();
	__DSB();
	u32CycStop = DWT->CYCCNT;

__enable_irq();

 

I'm not sure which memory barriers (ISB, DMB, DSB) are really required - but it makes a difference to use some at all. I recently checked some multiplication vs bit shift speed, and without the memory barriers the speed was unrealistically low (factor of 4).

 

[Ozone]

>> This is the first time I ever heard about limited uC lifetime.
>> This made me wonder if newer ST uCs are less reliable if running at nominal CPU speed.

> Same here! :D

Not for me.

Especially when the Pentium-4 raised PC power requirements to insane levels about two decades ago, heat-related failures became more frequent. And besides the exploding LV supply rail caps, processors began to suffer from "heat strokes" and related damages as well. Most modern processors, especially not of the x86 kind, would survive an hour without thermal throttling.

And high-end MCUs like the H7 are moving into this direction - and will eventually need to take the same precautions.