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December 26, 2023
Solved

Having Issues with ADC configuration STM32L011K4T6

  • December 26, 2023
  • 2 replies
  • 1775 views

Hello,

 

 

I have tried for the last couple of days to get use 2 pots to change the frequency and duty cycle of a PWM signal using "Bare Metal" programming due to the flash limitation of the STM32L011K4T6 I rapidly ran out of space using HAL and was not able to make this fit. I am using the STM32 Nucleo-L011K4 Board

 

The Issue I am having is under HAL I got the STM32L011K4T6 to read from 1 Pot and output a variable frequency PWM signal or 2 Pots and no PWM Signal due to size limitations. So I switched to Bare Metal Programming and have had nothing but issues even though I set the registers the same and have followed multiple different guides online but every time I wait for the ADC_ISR_EOC flag to be set it gets set as soon as I trigger ADC_CR_ADCSTART but then disappears as soon as I get into the while variable so it forms an infinite loop.

at this point I do not know what I am doing wrong.

 

Any help would be greatly appreciated. 

Code Below

uint32_t freq = 0;
float dc = 0;

int main(void)
{
 HAL_Init();
 SystemClock_Config();
 MX_GPIO_Init();
 MX_ADC_Init();
 MX_TIM2_Init();
 HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_1);
 ADC1->CR |= ( ADC_CR_ADVREGEN );
 HAL_ADCEx_Calibration_Start(&hadc,ADC_SINGLE_ENDED);
 if (1)
 {
 ADC1->CR |= ( ADC_CR_ADCAL );
 while ( ADC1->CR & ADC_CR_ADCAL ) {};
 }
 while (1)
 {
 ADC1->CHSELR = 0;
 ADC1->CHSELR |= ADC_CHSELR_CHSEL3;	 
 ADC1->CR |= ADC_CR_ADEN;
	 ADC1->CR |= ADC_CR_ADSTART;
	 while(!(ADC1->ISR & ADC_ISR_EOC)){}
	 freq = ADC1->DR;
	 ADC1->CR &= ADC_CR_ADSTART;

	 ADC1->CHSELR = 0;
	 ADC1->CHSELR |= ADC_CHSELR_CHSEL7;
	 ADC1->CR |= ADC_CR_ADEN;
	 ADC1->CR |= ADC_CR_ADSTART;
	 while(!(ADC1->ISR & ADC_ISR_EOC)){int a = a;}
	 dc = ADC1->DR;
	 ADC1->CR &= ADC_CR_ADEN;
	 ADC1->CR &= ADC_CR_ADSTART;
	 dc = (dc - 0.0) * (4095.0 - 0.0) / (4095.0 - 0.0) + 0.0;
 freq = freq * 65535;
 freq = freq / 4095;
 if(dc <= freq)
 {
		 TIM2->ARR = freq - 1;
		 TIM2->CCR1 = (freq / dc);
 }
 }
}




void MX_GPIO_Init(void)
{
	GPIOA->MODER |= (3 << (3*2));
	GPIOA->MODER |= (3 << (7*2));
}




/**
 * @brief System Clock Configuration
 * @retval None
 */
void SystemClock_Config(void)
{
 RCC->CR = 0x3000305;
 RCC->AHBENR = 0x100;
 RCC->APB2ENR = 0x400201;
 RCC->APB1ENR = 0x10000001;
 RCC->IOPENR = 0x5;
}


static void MX_ADC_Init(void)
{
	RCC->APB2ENR |= (RCC_APB2ENR_ADCEN);
	/*
	ADC1->CR &= ~ADC_CR_ADVREGEN;
	for(int i =0;i<10*48/4;i++){i=i;}
	ADC1->CR |= ADC_CR_ADVREGEN;
	ADC1->CR |= ADC_CR_ADCAL;
	while((ADC1->CR & ADC_CR_ADCAL) != 0){int a = a;}
	ADC1->CFGR2 &= ~ADC_CFGR2_CKMODE;
	ADC->CCR |= ADC_CCR_TSEN;
	ADC1->CHSELR |= (1 << 3);
	ADC1->CHSELR |= (1 << 7);
//	ADC1->CR = 0x10000000;
//	ADC1->CFGR1 = 0;
//	ADC1->CFGR2 = 0x40000000;
	ADC1->SMPR = 0x2;*/
}


static void MX_TIM2_Init(void)
{
	TIM2->CR1 = 0x281;
	TIM2->SR = 0x1f;
	TIM2->CCMR1 = 0x68;
	TIM2->CCER = 0x1;
	TIM2->PSC = 0x14;
	TIM2->DMAR = 0x281;
}

 

    This topic has been closed for replies.
    Best answer by ONadr.1

    Optimizing is in main menu. Navigation is:

    Project-->Properties-->C/C++Build-->Settings-->MCU GCC Compiler-->Optimization

    and here settings Optimization level  --> Optimize for size (-Os)

    2 replies

    Graduate
    December 26, 2023

    When you used HAL, did you try to optimize the compiler for code size? I had a similar problem and after turning on optimization, the volume decreased by a third.

    Explorer
    December 26, 2023

    I did try to follow guides on how to optimize the compiler but most of it was out of date and most were conflicting and confusing. if it helps I am using STM32cubeIDE Version 1.13.2. But yeah I was still 3Kb over the flash storage.

    If it helps just so you do not have to look for the specs it has 16kb flash and 2kb ram.

     

    ONadr.1Answer
    Graduate
    December 26, 2023

    Optimizing is in main menu. Navigation is:

    Project-->Properties-->C/C++Build-->Settings-->MCU GCC Compiler-->Optimization

    and here settings Optimization level  --> Optimize for size (-Os)

    Super User
    December 26, 2023

    > ADC1->CR &= ADC_CR_ADSTART;

    This clears all flags except ADSTART. You probably want:

    ADC1->CR &= ~ADC_CR_ADSTART;

     

    Consider using SET_BIT and CLEAR_BIT instead to avoid typos like that.