High & Low logic level thresholds vs Rise Time measurement points

[fujiangmu]

Why is the high level range 0.7VDD~VDD and the low level range 0.3VDD~VSS in Table 21 of STM32F103xC, STM32F103xD, STM32F103xE (DS5792 Rev 13), while the rise time in Figure 19 ranges from 10% to 90%?

 

[Danish1]

Are you clear on what ST mean by 10% to 90%? 10% to 90% of what?

Looking at the graph, it seems clear to me that 0% is Vhsel (i.e. 0.3 of Vdd, so around 1V) and 100% is Vhseh (0.7 of Vdd, so around 2.3V)

So ST are saying the waveform has to go from below 1V to above 2.3V, and the transition between 1.2V and 2.1V must be quick.

[fujiangmu]

You mean 1.2V=10%*|Vhsel-Vhseh|+0.3VDD and 2.1V=90%*|Vhsel-Vhseh|+0.7VDD ?

But why is the rise time in Figure43 (IIC) from 0.3VDD to 0.7VDD?

 

[Andrew Neil]

Why not?

It is pretty standard practice across the industry to specify risetime between the 10% and 90% points

https://en.wikipedia.org/wiki/Rise_time#:~:text=these%20percentages%20are%20commonly%20the%2010%25%20and%2090%25%20(or%20equivalently%200.1%20and%200.9)%20of%20the%20output%20step%20height

As the name suggests, it's just about the rate of rise - it really has nothing to do with the logic level thresholds.

[fujiangmu]

Sorry, I can't open the website.

In IIC , the rise time is from 30% to 70%. You can see this in Figure43 of <STM32F103xC, STM32F103xD, STM32F103xE (DS5792 Rev 13)>. But according to what you mean, the maximum of the rise time in IIC  is from 10% to 90%?

[Andrew Neil]

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@fujiangmu wrote:

Sorry, I can't open the website.

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@fujiangmu wrote:

But according to what you mean, the maximum of the rise time in IIC  is from 10% to 90%?

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No, you're missing the point.

The point is that the points used to measure rise time are arbitrary - they are not related to the logic level thresholds.

Rise time is about speed - not levels.