How to connect 8 SRAMs to STM32H7

[kazutobi]

Hello everyone.

I want to connect 8 SRAMs (2MB) to STM32H755XIH3 and use them as 16MB work memory.

When connecting 8 memories (SRAMs) using FMC (devices more than the number of FMC_NE*), how should I connect and control them? If there are any similar cases, I would appreciate your advice.

 

I am currently considering it, but I have some conditions.

1. I will use Infenion's CY7C1061GE30-10BVJXIT (2MB) with dual chip enable for the SRAM.

2. Of the 4 NEs in the FMC, 2 will be used to connect other memories, so only 2 can be used for SRAM.

Thank you in advance.

[LCE]

I wonder WHY do you want to do that?

The PCB routing alone calls for trouble... 8 BGAs sharing more than 30 data address and data lines, then think of the IO capacitance of each IC. 

No real help, but unless you have something very smart and specific on your mind, rather go for a bigger FMC SRAM, or use a HyperRam via OCTOSPI.

[mƎALLEm]

Hello,

Too complicated solution. But why are you using 8 SRAM memories when you can do it with one of 16MB?

As said by @LCE the PCB will be complex as well as the signal integrity and the IO capacitance.

From my standpoint, forget about this solution. It will bring you head ache more than what it brings as "solutions" .

[kazutobi]

Hi LCE, SofLit,

Thank you very much for your reply.

I need high-speed access and would like to use memory with ECC function, and I need 16MByte, so I will use 8 SRAM (2Mbit).

I don't think there is any SRAM with a capacity of more than 2Mbit, but it may be that I just haven't found it yet.

Thank you in advance.

[kazutobi]

Sorry, that was a typo.

2Mbit--> 16Mbit

SRAM capacity is 16Mbit

[LCE]

Will you do the PCB layout, or do you want to annoy someone else? ;)

You will lose a lot of your envisioned "high speed access" simply by adding up the PCB trace and IO capacitance.

And unless you may use via in pad methods, you will create a lot of trace stubs, another thing that signal integrity will suffer from.

I'm using an Infineon 16 MB HyperRAM at 100 MHz via OCTOSPI of an STM32H733, I get a data rate both read and write > 50 MB / s.
I can't imagine that you will be able to reach that.
But I'll be happy if you will prove me wrong! :)

[kazutobi]

Hello LCE

Thank you for your reply.

It was very helpful for you to share your experience.

I will reconsider this over the weekend.

[mƎALLEm]

I also add you may face IO current source issue as 8 memories will be driven in parallel.

Mostly the control lines: WR/ OE etc ..

[Tesla DeLorean]

You'd need to use 3 of the high order address bits to create a 3-to-8 decoder to generate chip selects for the individual memories. 

[kazutobi]

Hello Tesla DeLorean
Thank you for your reply.
The SRAM I'm trying to use has two chip enable terminals.
I was thinking of doing it without a decoder. I don't know if that's possible though.

[mƎALLEm]

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@kazutobi wrote:

The SRAM I'm trying to use has two chip enable terminals.
I was thinking of doing it without a decoder. I don't know if that's possible though.

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Two chip enable is to enable the memory itself.  You need to use one and fix the another. You need as @Tesla DeLorean said an address decoder like the old TTL "74138" to address 8 memories. Each 74138 output will drive a chip enable of a memory. The address decoder is driven by the Higher address lines.

This is an old concept. So for example this link: https://ece-research.unm.edu/jimp/310/slides/8086_memory2.html