How to enable Fast Mode Plus(Fm+) for I2C on STM32L496?

[ANath.1]

I'm trying to configure the I2C to run at 1Mhz(Fm+) on STM32L496. As per the RM0351, it does support fast mode plus mode. I tried generating the code from STM32Cube IDE and check the SCL pin of logic analyzer. However, I see 400 khz I2C clock frequency. How do I achieve 1Mhz I2C clock?

Configurations:

I2C peripheral: I2C2

I2C clock source: SYSCLK

SYSCLK freq: 80Mhz

Code generated:

/** I2C Initialization
 */
 LL_I2C_EnableAutoEndMode(I2C2);
 LL_I2C_DisableOwnAddress2(I2C2);
 LL_I2C_DisableGeneralCall(I2C2);
 LL_I2C_EnableClockStretching(I2C2);
 I2C_InitStruct.PeripheralMode = LL_I2C_MODE_I2C;
 I2C_InitStruct.Timing = 0x00B0122F;
 //I2C_InitStruct.Timing = 8459040;
 I2C_InitStruct.AnalogFilter = LL_I2C_ANALOGFILTER_DISABLE;
 I2C_InitStruct.DigitalFilter = 0;
 I2C_InitStruct.OwnAddress1 = 0;
 I2C_InitStruct.TypeAcknowledge = LL_I2C_ACK;
 I2C_InitStruct.OwnAddrSize = LL_I2C_OWNADDRESS1_7BIT;
 LL_I2C_Init(I2C2, &I2C_InitStruct);
 LL_I2C_SetOwnAddress2(I2C2, 0, LL_I2C_OWNADDRESS2_NOMASK);
 /** I2C Fast mode Plus enable
 */
 LL_SYSCFG_EnableFastModePlus(LL_SYSCFG_I2C_FASTMODEPLUS_I2C2);
 

However, I see only 400khz on logic analyzer. Can someone help where I might be getting it wrong?

I'd also like to understand how the timing register value is calculated. I didn't get much from RM. They say use STM32Cube IDE for accurate values.

Thanks,

Abhijit Nathwani

[Bubbles]

Hi @ANath.1​ ,

the system clock may be 80MHz, but what clock is configured for the I2C peripheral?

In the RM0351 there is an example configuration of working 1MHz timing settings with 16MHz peripheral clock.

BR,

J

[ANath.1]

Hi @JHOUD​ 

As I mentioned in the post, the I2C clock source is SYSCLK(80 Mhz).

As per your recommendation, I tried to replicate the settings shared in RM0351 for Fm+ mode. However, I still see the same behavior.

I2C clock source set to HSI clock running at 16Mhz.

Based on the values in the table above:

PRESC = 0x0

SCLL = 0x4

SCLH = 0x2

SDADEL = 0x0

SCLDEL = 0x2

This values the timing register value as 0x00200204

I set this as custom timing in the CubeIDE however the behaviour is still the same.

[ANath.1]

Hi All,

Appreciate some hints on this issue. Been looking for a solution for a long time.

[Wireless Support Team - OZ]

I have just come across to the post. Since it is Fm+, did you try relatively lower value pull-up resistors (depends on the bus length/the bus capacitance) like 2K2? The max. rise time of both SDA and SCL signals is 120ns for Fm+ comparing 300ns for Fm and 1000ns for standard mode. So, adjusting the pull-ups solves the speed issues in some cases like yours.

 

Best Regards