How to flush cache in CubeF7 Flash EraseProgram example?

[osiris81]

In the CubeF4 Flash EraseProgram example (STM32F4-Discovery/Examples/FLASH) there is this section after the erase:

/* Note: If an erase operation in Flash memory also concerns data in the data or instruction cache,
 you have to make sure that these data are rewritten before they are accessed during code
 execution. If this cannot be done safely, it is recommended to flush the caches by setting the
 DCRST and ICRST bits in the FLASH_CR register. */
 __HAL_FLASH_DATA_CACHE_DISABLE();
 __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
 
 __HAL_FLASH_DATA_CACHE_RESET();
 __HAL_FLASH_INSTRUCTION_CACHE_RESET();
 
 __HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
 __HAL_FLASH_DATA_CACHE_ENABLE();

In the same example in CubeF7 (STM32F769I-Discovery/Examples/FLASH), there is the same note, but before the erase and with no code at all:

/* Note: If an erase operation in Flash memory also concerns data in the data or instruction cache,
 you have to make sure that these data are rewritten before they are accessed during code
 execution. If this cannot be done safely, it is recommended to flush the caches by setting the
 DCRST and ICRST bits in the FLASH_CR register. */
 if (HAL_FLASHEx_Erase(&EraseInitStruct, &SECTORError) != HAL_OK)
 {

In the examples for other stm32f7 boards there is no note at all... Is there some flush necessary for the stm32f7 or is this note just a copy paste error?

[H7]

Any updates on this topic?

I ran into the same issue.

[Tesla DeLorean]

Yes, you're going to have to manage cache-coherency. All the stuff you learned about cache architecture would be prescient here. Review CM7 TRM.

You'd honestly do better doing flash work while the cache isn't enabled, or setting the MPU up to exclude the area in question.

If you do a blanket cache invalidate you'll likely crash the system.

[jbake_uni]

For stm32f7:

Information i have to go by on is:

 

HAL_StatusTypeDef HAL_Init (void )

This function is used to initialize the HAL Library; it must be the first instruction to be executed in the main program (before to call any other HAL function), it performs the following: Configure the Flash prefetch, and instruction cache through ART accelerator.

 

 

There is a document:

Cortex®-M7 cache maintenance operations using CMSIS ia in PM0253.

https://www.st.com/resource/en/application_note/an4839-level-1-cache-on-stm32f7-series-and-stm32h7-series-stmicroelectronics.pdf

 

you can look in the file core_cm7.h.

I think these work well with me. You can look at how the drivers work and craft your own.

 

and

um1905-description-of-stm32f7-hal-and-lowlayer-drivers

look in  HAL FLASH Generic Driver section for some info. 

 

This works for stm32f411re  example for a flush:

 

static void flush_caches(void)

{

/*Flush instruction cache*/

  if (READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != RESET)

  {

    /* Disable instruction cache  */

  FLASH->ACR &= (~FLASH_ACR_ICEN);

 

/* Reset instruction cache */

  FLASH->ACR |= FLASH_ACR_ICRST;

FLASH->ACR &= ~FLASH_ACR_ICRST;

 

 

/* Enable instruction cache */

FLASH->ACR |= FLASH_ACR_ICEN;

  }

 

  /*Flush data cache*/

 

  if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET)

  {

    /* Disable data cache  */

  FLASH->ACR &= (~FLASH_ACR_DCEN);

 

    /* Reset data cache */

    FLASH->ACR |= FLASH_ACR_DCRST;

    FLASH->ACR &= ~FLASH_ACR_DCRST;

 

    /* Enable data cache */

    FLASH->ACR |= FLASH_ACR_DCEN;

  }

}

 

[jbake_uni]

based on previous info:

 

for stm32f7 this seams like it would do the trick.

 

static void flush_caches(void)

{

SCB_EnableICache(); //Invalidate and then enable the instruction cache

 

SCB_EnableDCache(); //Invalidate and then enable the data cache

}