How to make sure CRC has the 4 AHB clock cycles processing time it needs?

[F71334]

Hello,

in the Reference Manual of STM32H745/755 and STM32H747/757 (RM0399) on page 831:

When I write more than two 32 bit words to the CRC data register, how can I ensure the crc unit has enough time for the calculation (the 4 AHB clock cycles) before I write the next word? The CRC unit has no "BSY" or "RDY" bits. Do I have to estimate/calculate the time I have to wait between two writes? Or is there some kind of blocking mechanism that prevents a write to the data register before the unit is ready to process the next word? If yes, what exactly is blocked: code execution in general, because the write is stalled?

Thanks for any information.

F

[waclawek.jan]

The "original" CRC module stalled the writes (inserted waitstates to the bus master which attempted the write) for the subsequent write until the previously written value passed through the calculation. That effectively meant that you did not need to care about the calculation duration, just simply write to CRC_DR, the wait happened automatically when needed.

I guess with this new CRC module it's the same, except that there is one extra write buffer added.

I am not ST, though; and yes, this ought to be documented properly.

JW