HSISYS Divider and RCC_CFGR Description in RM0503 (STM32U0)
Hello,
I have two questions regarding the STM32U0 series and the RM0503 reference manual:
1/ HSISYS Divider Configuration
In RM0503, for the STM32U0 series, it is stated that HSISYS is a clock derived from HSI16 after division by a value from 1 to 128.
This is shown in Figure 11: Clock Tree (page 157).
However, there appears to be no field in the RCC registers to configure this divider.
In the "STM32U0 – RCC Reset and Clock Controller" presentation, an HSIDIV value is mentioned, but this name does not appear anywhere in the RM.
The only potentially related fields are HSITRIM and HSICAL in the RCC_ICSCR register, but as far as I understand, these do not perform frequency division in the traditional sense.
Could you clarify whether the HSIDIV functionality is present in STM32U0 and, if so, how it is configured?
2/ Inconsistency in RCC_CFGR Description (SW Field)
In the RCC_CFGR register description for the SW field, the RM states:
"The setting is forced by hardware to 000 (HSISYS selected) when the MCU exits Stop, Standby, or Shutdown mode, or when the setting is 001 (HSE selected) and HSE oscillator failure is detected."
However, just above that, the bit values are described as:
000: MSI
001: HSI
This seems contradictory. Could you clarify whether the value 000 corresponds to MSI or HSISYS, and whether this is an error in the documentation?
Best,
msemegen