HYPERBUS

[K_I]

I am using the OCTSPI1 of STM32L4Q5CGTX to set HYPERRAM to memory-mapped mode.
Memory can be read and written correctly.
When I use STM32CubeIDE to check the HYPERBUS signals with an oscilloscope while the CPU is stopped with a break during program execution, CS# periodically becomes active, RWDS becomes HIGH during the CA section, and a clock is also output. Why does memory-mapped mode drive the HYPERBUS even when HYPERRAM is not being accessed? Is this a HYPERBUS specification?

Can anyone answer this question?
Thank you in advance.

[Ozone]

A kind of DRAM that requires regular refresh cycles ?

[K_I]

Thank you for your reply.

The HYPERRAM I'm using automatically starts refreshing when CS# is not active. It is a type that does not require instructions from the host.
Thank you in advance.