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January 31, 2024
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I have a problem of using SPI in STM32H753VIT6 CHIP

  • January 31, 2024
  • 2 replies
  • 6488 views

Hello,

I'm trying to do SPI communication with an ADE1201 chip through an STM32H753VIT6 chip.

The maximum allowed frequency of the ADE1201 is 10MHZ, so I set the SPI to communicate with the MCU at 6.25MHZ.

(The clock for SPI communication is 25MHZ, and I set the PRESCALER value to 4).

However, a strange phenomenon was observed.

화면 캡처 2024-01-31 133410.png

I observed through the scope that the SPI CS signal should be 0 continuously, but it turns to 1 in the middle.(See attached photo).

However, if I set the PRESCALER value to 8, the CS signal is continuously output as 0.

 

What could be the cause? And how can I solve this?

Could this be due to the usage of HAL_SPI_TransmitReceive function?

 

    This topic has been closed for replies.
    Best answer by Pierre_Paris

    Hello @KDG ,

    As I can see, here some remarks :

    • You declares NSSPMode to SPI_NSS_PULSE_ENABLE. This mode is activated by the SSOM bit in the SPIx_CR2 register. For SSOM = 1, SPI data frames are interleaved with SS non active pulses when MIDI[3:0]>1. That's explaining the behavior of your SPI4 CS line. According to RM0433, we are in a situation quite similar as shown in figure 620.Pierre_P_0-1706785910666.pngCan you change to SPI_NSS_PULSE_DISABLE ? Does that solve your issue ? 
    • It's recommended to set MasterKeepIOState to SPI_MASTER_KEEP_IO_STATE_ENABLE to avoid glitches.

    Best Regards,

    Pierre

    2 replies

    ST Employee
    January 31, 2024

    Hello @KDG,

    Thank you for your question !

    Here some remark :

    • Can you share your code ? At least your SPI parameter configuration and what API you called (HAL_SPI_TransmitReceive, that's it?)
    • When prescaler = 8 (f = 3.12 MHz), the behavior is normal but when prescaler = 4 (f = 6.25MHz), there is sometimes the CS which turns to 1. This is the only change you made between both screen right ?
    • Also, do you have the values of registers ? SPI_CFG1 ? SPI_CFG2 (especially SSOE, SSOM & SSM) ? In master mode, the SS can be used either as an output or an input. As an input it can prevent a multi master bus collision, and as an output it can drive a slave select signal of a single slave. How many masters are on the bus ? 

    Kind Regards,

    Pierre

    KDGAuthor
    Explorer
    February 1, 2024

    Thanks for the remark @Pierre_Paris 

     

    These are the answers for your remarks

    • static void MX_SPI4_Init(void)
      {

      /* USER CODE BEGIN SPI4_Init 0 */

      /* USER CODE END SPI4_Init 0 */

      /* USER CODE BEGIN SPI4_Init 1 */

      /* USER CODE END SPI4_Init 1 */
      /* SPI4 parameter configuration*/
      hspi4.Instance = SPI4;
      hspi4.Init.Mode = SPI_MODE_MASTER;
      hspi4.Init.Direction = SPI_DIRECTION_2LINES;
      hspi4.Init.DataSize = SPI_DATASIZE_8BIT;
      hspi4.Init.CLKPolarity = SPI_POLARITY_HIGH;
      hspi4.Init.CLKPhase = SPI_PHASE_2EDGE;
      hspi4.Init.NSS = SPI_NSS_HARD_OUTPUT;
      hspi4.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_4;
      hspi4.Init.FirstBit = SPI_FIRSTBIT_MSB;
      hspi4.Init.TIMode = SPI_TIMODE_DISABLE;
      hspi4.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
      hspi4.Init.CRCPolynomial = 0x0;
      hspi4.Init.NSSPMode = SPI_NSS_PULSE_ENABLE;
      hspi4.Init.NSSPolarity = SPI_NSS_POLARITY_LOW;
      hspi4.Init.FifoThreshold = SPI_FIFO_THRESHOLD_01DATA;
      hspi4.Init.TxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN;
      hspi4.Init.RxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN;
      hspi4.Init.MasterSSIdleness = SPI_MASTER_SS_IDLENESS_00CYCLE;
      hspi4.Init.MasterInterDataIdleness = SPI_MASTER_INTERDATA_IDLENESS_00CYCLE;
      hspi4.Init.MasterReceiverAutoSusp = SPI_MASTER_RX_AUTOSUSP_DISABLE;
      hspi4.Init.MasterKeepIOState = SPI_MASTER_KEEP_IO_STATE_DISABLE;
      hspi4.Init.IOSwap = SPI_IO_SWAP_DISABLE;
      if (HAL_SPI_Init(&hspi4) != HAL_OK)
      {
      Error_Handler();
      }
      /* USER CODE BEGIN SPI4_Init 2 */

      /* USER CODE END SPI4_Init 2 */

      }

      And the API IS
      HAL_SPI_TransmitReceive(&hspi4, u8_R_head_buffer, u8_R_buffer, 4 , 10 );
    • Yes, that is the only change made between both screeen

    • These are the values for the registers that you required
      • 화면 캡처 2024-02-01 093803.png

      • There are only one master on the bus


    I wonder if this would be enough for your remarks.

    Thank you.

    Sincerely,

    KDG

    ST Employee
    February 1, 2024

    Hello @KDG ,

    As I can see, here some remarks :

    • You declares NSSPMode to SPI_NSS_PULSE_ENABLE. This mode is activated by the SSOM bit in the SPIx_CR2 register. For SSOM = 1, SPI data frames are interleaved with SS non active pulses when MIDI[3:0]>1. That's explaining the behavior of your SPI4 CS line. According to RM0433, we are in a situation quite similar as shown in figure 620.Pierre_P_0-1706785910666.pngCan you change to SPI_NSS_PULSE_DISABLE ? Does that solve your issue ? 
    • It's recommended to set MasterKeepIOState to SPI_MASTER_KEEP_IO_STATE_ENABLE to avoid glitches.

    Best Regards,

    Pierre

    KDGAuthor
    Explorer
    February 2, 2024

    Thanks @Pierre_Paris 

    By your remarks, my problem is solved.