I2C reads FF and stucks

[malb0794]

Hi everyone! 

I'm using two uC, STM32F105VCT7TR and MSP430G2452, and I'm establishong an I2C communication between them, with the STM32F105 being the master and MSP430 the slave. For the write operation, the communication works fine. However, when performing a read operation, things do not go as expected - I can't read the data (every time I get FF data) and the bus gets stuck.

Here's what I'm doing to read the MSP data.

 

Here's the scope.

 

Could anyone help me, please?

[Geek09]

Did you check your hardware setup ?Maybe try reading from different register or reading different number of bytes to eliminate possibilities?

[malb0794]

Yes, I already checked the hardware and tried reading another register.

The hardware is adequate and even changing the register or the number of bytes it is not possible to read it.

[waclawek.jan]

For the single-byte read, you have to clear I2C_CR1.ACK *before* clearing ADDR.

Read and follow "Method 2" in "Master receiver" subchapter in I2C chapter in RM0008, there are 3 distinct cases: for 1, 2, and more read bytes.

JW

 

[malb0794]

I had followed what is written in the reference manual, but I couldn't read it either.

Clearing the ACK as suggested keeps reading FF, but now SDA stays high and SCL gets stuck low.

[AScha.3]

Just looking at your scope pic , i see two problems :

- signal levels 4Vss  --- how can this be real?  3,3V is max. with 3,3V cpu !

- SDA shows 3 (!!!) voltage levels - nothing, that a I2C can ever do - if hardware ok.

 

+

Is this on both chips I2C , open drain ? + pullups ? 

What value are pullups ? 

[malb0794]

The hardware is OK.

Boths uC are configured correctly.

The value of the pullups is 2k2.

[waclawek.jan]

> SDA shows 3 (!!!) voltage levels - nothing, that a I2C can ever do - if hardware ok.

This is consequence of a small series resistor in SDA, a common trick to distinguish master and slave when looking at the waveforms on an oscilloscope.

JW

[AScha.3]

Clever !

But still : 4V level - why ?  (3,6 is typ. max .)

+

>This is consequence of a small series resistor in SDA

ok, but here seem the "3." level generated by the "helping" resistor close to 1V above gnd, so this might be close to wrong 0->1 decision .... right ?  ( try without these resistor ... same effects ?)

[waclawek.jan]

> Clearing the ACK as suggested keeps reading FF,

That's what your slave reads from that address. As the waveform shows, the next byte would read non-FF.

> but now SDA stays high and SCL gets stuck low.

This to me sounds like clock stretching due to missing STOP.

JW

 

[malb0794]

Hi everyone! 

I managed to read the data following the application note AN2824 (Figure 2, with N = 2). 

However, I can only perform one reading because, after the reading is finished, it is no longer possible to send the START.

 

[waclawek.jan]

What's content of status registers at that point?

Also note, that debugging is intrusive, and looking at the registers in debugger may change the internal state machine's state.

JW

[malb0794]

I needed to take a little trip, I won't be able to check until next week. 

As soon as I arrive, I will send a print with the status of the I2C-related registers.

However, there is a change only in registering DR and CR1. In CR1 I cannot set the ACK bit at the end and the PE bit is cleared after setting the POS bit, making it impossible to set it or start a new communication, as the START is not generated.

Below the code used.