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K
KAgga.1
Visitor II
April 4, 2024
Question

Infrequently getting UNALIGNED HardFault

  • April 4, 2024
  • 1 reply
  • 1094 views

Hello There,

I'm working on a FREERTOS based STM32H7A3 application.
Upon debugging, my code randomly halts on UNALIGNED hardfault. The occurrence of this fault condition is very rare. During my testing in the last 30days, I ran into this for nearly 3 times with no clue of the source of this fault.

Attaching some screenshots from the last debug session.

Call Stack

KAgga1_0-1712212064993.png

 

Fault Analyzer

KAgga1_1-1712212107019.png

 

FreeRTOS Task List

KAgga1_2-1712212277969.png

I also noticed in the FreeRTOS Task List, some Event Objects (marked in RED) showing corrupted addresses.

 

FreeRTOS Semaphores

KAgga1_3-1712212424110.png

I also noticed some unwanted characters present at the end of Semaphore name. It must be "appSysTaskInit" (Marked in Red).

 

Memory Area (Flash.ld)

MEMORY
{
 ITCMRAM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K
 FLASH (rx) : ORIGIN = 0x08020000, LENGTH = 960K
 DTCMRAM1 (xrw) : ORIGIN = 0x20000000, LENGTH = 64K
 DTCMRAM2 (xrw) : ORIGIN = 0x20010000, LENGTH = 64K
 DISP_FB (rw) : ORIGIN = 0x24000000, LENGTH = 150K
 RAM (xrw) : ORIGIN = 0x24025800, LENGTH = 874K
 RAM_CD (xrw) : ORIGIN = 0x30000000, LENGTH = 128K
 RAM_SRD (xrw) : ORIGIN = 0x38000000, LENGTH = 32K
}

 

Thanks for taking time to read this post.

Any help is appreciated to get to know the source of the fault.

Regards,

Keshav Aggarwal

 

 

 

 

    This topic has been closed for replies.

    1 reply

    T
    Tesla DeLorean
    Graduate II
    April 4, 2024

    Probably going to want to check the flow dynamics immediately prior to the failures, try to understand some commonality in the behavior. 

    Would suggest adding some sanity checking of the impacted structures so you can quickly see when things start to go wrong. Might occur more often, and then just faults when doing 64-bit LDRD / STRD against misaligned pointers.

    Using DMA or Invalidate DCache operations?

    K
    KAgga.1Author
    Visitor II
    April 4, 2024

    Thanks for your reply!
    Yes, I'm using DMA & Invalidate DCache operations. DMA being used continuously to transfer the pixels to Display frame buffer. (Frame Buffer is residing in Internal RAM) 

    DISP_FB (rw) : ORIGIN = 0x24000000, LENGTH = 150K

    I'm also attaching .ioc file if you want to have a look.

    Regards,
    KA

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