Interfacing the LTC1403 SPI ADC

[always_energized]

Hi there,

I'm currently trying to get SPI Communication with the LTC1403 up and running, however I'm struggling with the timing of the Conv Signal.It seems like I need the rising edge of SCK at the same time as the Conv Signal is high. How can I achieve this? Some Pseudo Code would already help me a lot.

The Conv signal is currently connected to the hardware NSS Signal, maybe connecting it to a timer output would have been smarter?

[TDK]

> How can I achieve this?

Don't think you can.

TI mode does what you want except that the polarity is wrong and unable to be changed. Don't think any other options have SCK active while SS is in the inactive state.

 

Using a timer for CONV and possibly for SCK as well to get tighter timing adjustability could work but likely requires a hardware change.

[Pavel A.]

From the document, it is not obvious that SCK edge must coincide with CONV and that CONV has any relation to the NSS of the SPI at all. See page 15: "... interface has been designed for high speed buffered serial ports in fast digital signal processors (DSPs)." As example they quote a TMS320. Analog Devices support  can advice on translation of this for STM32H7 and SPI. The code they provide in the document (in TMS320 assembler language) doesn't make much sense for STM32.

 

[MasterT]

IMHO, all confusion comes due very outdated serial interface design. Likely before SPI protocol becomes fully specified. 

So I 'd simply ignore all those SCLK pulse #1 requirements, basically omit #1 as useless noise source, making CS (CONV) wider - two periods or so and clock 17 as necessary for conversion logic. 

Lucky H7 can generate CS by SPI in DMA mode, all you have to do is adjust width of CS to have the best SNR vs sampling rate.