IO Cell compensation not working/insufficient data available

[Robmar]

In the RM for the H743 there is little information about using IO cell compensation aimed at reducing noise on VDD and EMI radiated.

Posts show the following calls to active:-

__HAL_RCC_CSI_ENABLE();

__HAL_RCC_SYSCFG_CLK_ENABLE();

HAL_EnableCompensationCell();

The RM briefly mentions values for PMOS and NMOS transistors to presumably control slew rates, but I cannot find any data on how to determine the bit values.

There is a function, HAL_SYSCFG_CompensationCodeSelect(), but again there are no examples of its use.  Google also shows no example code!

I have tested the sample code posted on this forum but it does nothing noticeable to reduce noise on the VDD line.

Is more information available about how to reduce noise via slew rate adjustment?

Hello STM staff, is there anybody out there?

 

[STOne-32]

Dear @Robmar ,

We introduced I/O compensation cell for our first 90nm Process technology for STM32F2 and F4 and then we maintained it for high speed and high performance lines such as H7 and recent platforms. Basically we can summarize this feature ( design process - not easy to see the impact for typical devices ) that it operates in opposite way as I/O digital Output speed and will reduce and compensate the fast process ( fast transistors) in automatic way for user . For more details see this slide 8 

https://www.st.com/content/ccc/resource/training/technical/product_training/group0/29/35/ae/de/59/26/4c/e4/STM32H7-System-General-purpose_IO_interface_GPIO/files/STM32H7-System-General-purpose_IO_interface_GPIO.pdf/_jcr_content/translations/en.STM32H7-System-General-purpose_IO_interface_GPIO.pdf

And this from STM32F4 series .

by the way it is a good idea to have a knowledge base on the topic !

hope it helps you .

STOne-32

[Robmar]

Okay, but none of that provides information on how to calculate the two settings to control the slew rates.

Can you tell me what settings, how to calculate them, so that my fast lines create less noise?

It mentions "automatic slew rate adjustment", but the two values for adjustment are also presented, so I don't know if I need to set them, and I don't know if there is a mechanism that automatically sets them, in which case why are they exposed to the programmer?

[STOne-32]

SW application do not have to know how to set that . It is internal hard block by design and sets in automatic way for user application. The most important to set the feature only .

[Robmar]

Sending me a copy of the standard manual page is UNHELPFUL.

This does now show what settings are needed, how to calculate the slew rate, does it?

[waclawek.jan]

> how to calculate the slew rate

You don't need to. As @STOne-32  said above, just leave it on the auto setting.

> why are they exposed to the programmer?

There's probably no practical reason for the user. Manufacturer may use it at the manufacturing testing.

> I have tested the sample code posted on this forum but it does nothing noticeable to reduce noise on the VDD line.

Then if you don't need it, keep it switched off.

JW

 

[STOne-32]

To observe an effect on these feature many conditions should be met :

• First it acts only on Output Rise/fall time to measure for example between 10% to 90% of VDD
• The selected part MCU should not be within the Gaussian of distribution out of our production that means extreme Slow or fast process . This will be seen only at huge production volume as we center well all shipped Part to our customers  - the chance is hundreds of PPM. ( parts per millions ) 

 STOne-32

[Robmar]

Again, that's not the information I requested.

I guess you don't know how to calculate the bit settings from the N and P-FET slew.

If anyone at STM has the information, please share, I'm sure people would like to know.