Is there any way to distinguish EXTI interrupt about its edge?

[Yang Yang]

Hello, ST experts

 

STM32F407 is used on our system. PE7 is configured as an EXTI pin for both rising and falling edge. How can I accurately  recognize which edge is the cause of this interrupt? Because there maybe a narrow glitch on PE7, so reading GPIO state on interrupt routine may not be a good way.

 

Best Regards

Yang

[Andrew Neil]

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@Yang Yang wrote:

Because there maybe a narrow glitch on PE7, so reading GPIO state on interrupt routine may not be a good way.

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In that case, why does it matter which edge actually caused the interrupt?

Anyhow, it would have been the first edge - surely?

[Yang Yang]

Hello，Andrew

 

Yes，it does matter which edge caused the interrupt. Different edges means different operations. Rising edge means pre-shutdown, falling edge means shutdown(at least 3 seconds interval).

By the way, think about this situation. Rising edge interrupt happened at 0 nano-second, but PE7 only keeps about 50 nano second, that means it goes low at 50 nano-seconds later. And interrupt routine clear the interrupt at about 1000 nano seconds later, is the falling edge interrupt ignored?

 

BR

Yang 

[Andrew Neil]

If it's really important to catch a glitch, maybe have two EXTIs - one rising, and one falling?

 

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@Yang Yang wrote:

Rising edge means pre-shutdown, falling edge means shutdown(at least 3 seconds interval). 

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In this case, you know that the rising edge has to happen first - so set EXTI just for that.

Once that rising edge has occurred, then start your timing for the 3-second interval...

basically a debounce operation...

 

[Ozone]

Usually by checking the line status in the interrupt routine.

In case of a glitch, as Andrew Neil suggested, you are most probably too late anyway.
And the timing is unpredictable.

If this is a problem for your application, add a glitch filter. 
This is usually a RC lowpass with a Schmitt trigger 

[Yang Yang]

Hello, Ozone

 

I am very apprecaited for your help. I will have a try about your suggestion. And as I said, the falling edge will be ignored at that situation?(falling edge happened after interrupt routine clears pending register)

 

BR

Yang

[Ozone]

I don't know your exact use case.
But you need to take system behavior in all plausible scenarios into account.
What happens if the second transition of a glitch happens before you even enter the interrupt (12 clk-cycle latency), or during the interrupt ?

Are those glitches of any relevance for your application, except of being an "annoyance" ?

As an example, all commercial ECUs we use have fixed or configurable glitch filters on DINs, defaulting to a 3dB frequency of a few kHz. Since our applications are based on a 10ms processing cycle, faster transitions/reactions are neither possible nor desired.
Other interfaces (like PWM or rotary encoders) are handled by specific peripherals, not software directly.

We have some self-designed legacy hardware designed in-house, which cause nothing but trouble in this regard.