IWDG Doesn't Reset Without Refreshing with F103RC

[Chao]

Hi,

I am trying to use IWDG to function as a 5s timer, IWDG is reloaded every second. In order to test the functionality, I just activated it with default parameters of PRESCALER=4 RELOAD VALUE=4095, and I did nothing else (no refreshing the timer), when I generate and build the code and run the main, no MCU reset occurs.

I checked an example with G070, except for the example measures the LSI frequency, it does not do extra things to get the IWDG work. The F1 RM says that the IWDG will automatically work once the  main starts working.

Where it's going wrong?

Regards

Chao

[Sarra.S]

Hello @Chao, 

Since you're configuring your clock source as LSE, I want to make sure you have a 32.768 kHz external crystal.

If not, you have to use LSI, this should work without issues. 

[Chao]

Hi Sarra,

Thanks for your reply!

Yes, I do have an external 32.768KHz crystal, but from my understanding of the clck tree I copied, the IDWG uses the LSI clock source in any cases as it comes straight from the 40KHz and not from the mux. 

The clock configuration in the CubeIDE example with G070 is as below:

Do you mean that I can't use both LSE and LSI. I have to use LSE for RTC, in this case how shoud I configure the clock for IWDG?

Regards

Chao

[TDK]

Debug the code, does it start the IWDG or does it get stuck somewhere before that?

[Chao]

Hi @TDK ,

Thanks for your reply!

I did do debugging, and could step through the Init code with HAL_IWDG_Init(&hiwdg) returns HAL_OK but my code runs as if the IWDG didn't exist:

I didn't refresh the counter and code runs as usual. The IWDG is a new functionality of my existing working code.

So any idea of this?

Regards

Chao

 

[Tesla DeLorean]

Does anything in your circuit drive NRST high with a push-pull driver?

Show your LSE circuit and component choices.

The F1's going to want a 6-7pF crystal, not the 9 or 12pF ones

Check LSE starts in normal usage via RCC, perhaps check via RTC TAMPER or wherever it routes out for testing.

[Chao]

Hi @Tesla DeLorean ,

The NRST and LSE circuit in our application is as below:

Signal RESET is routed to NRST Pin.

 

Signal O_IN32 and O_OUT32  are routed to OSC32_IN and OSC32_OUT, and they are not routed to anywhere else.

 

Regards

Chao