LSI Clock is very unsteady and cannot be reset in software

[Till Rachow]

Hi,

I stumbled across a problem with the LSI when i realized, that my IWDG was about 20% faster than it should be.

The clock is behaving very irregularly, this is more than the deviation in the datasheet. I read out the LSI from PA2 with an oscilloscope and attached the file. One division in the picture is 15.6us, so each division should be roughly one edge. You can see that some cycles are at roughly 64kHz, which of course is double the speed..

To reproduce this behaviour:

When connecting to power, unplug and plug the power very fast for a few times. The LSI will then enter this state and behave that way until power is unplugged and properly replugged.

Software reset and even flashing new software through our Bootloader did not have any effect, only after a power reset it will work fine again.

I saw this behaviour on 6 different boards so far.

I am using STM32L433CCTx with a custom designed hardware, supply voltage to the uC is 3.3V.

This is really worrying, also in terms of long term stability of the LSI.

Could the ST Team please let me know if you have seen this before? Maybe I could talk to someone from the development Team about this?

Thanks,

Till

[waclawek.jan]

Interesting, but 1. you'll be probably told to try to mitigate the problem first, with better decoupling/grounding/supply startup arrangement; 2. there's only a basic presence of ST here, you would want to contact them directly (through FAE or through the web support form).

JW

[waclawek.jan]

This is now erratum 2.2.7 Unstable LSI when it clocks RTC or CSS on LSE in ES0318 - Rev 4.

The same erratum is also in the 'H743 errata, so probably several STM32 families are affected.

JW

[waclawek.jan]

A recent discussion what is probably the same problem, here.

JW