LTDC double layer and double buffering + SDRAM
Hello,
i have TFT with resolution 800x480 @ 24bpp connected to the STM32F767BIT6 with external SDRAM IS42S16400J-7TL.
The MCU is running on 216MHz, thus FMC on 108MHz, SDRAM as CAS latency = 2 and LTDC pixel clock 19,2MHz(able to run on 24MHz too) with DMA2D. FMC is configured for switch address from 0xC000_0000 to 0x6000_0000 for posibility of cashing.
LTDC is configured to 2layers ARGB8888. The SDRAM has 4 banks and 16bit data bus, so 1st layer is located on start addres of 1st bank, 2nd layer is located on start address of 2nd bank. On 3rd and 4th bank i would like to have inactive buffers for 1st and 2nd layer.
In my experiment i fill 1st and 2nd layer located in 1st and 2nd bank with some graphic.
The screen on TFT is stable without any graphical artefacts.
But when i do some writes (let say 3KB) into 3rd or 4th bank once per 1second, the screen starts during writes having some graphical artefacts.
I think there is issue with SDRAM/FMC bandwith or bottleneck on FMC.
Is it feasible to have 800x480 24bpp with 2 layers and 2 buffers via one shared SDRAM running on 108MHz???
Is there any tip for raise the performance? If not, i will try to remove one layer and reduce data from ARGB888 to RGB565.
