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Petr3
Visitor II
March 9, 2024
Solved

LTDC problem

  • March 9, 2024
  • 2 replies
  • 2072 views

Hello,

i have problem with custom board assembled with STM32F767BIT6. I'm trying to interfacing LCD-TFT DEM 800480K3 TMH-PW-N which is assembled by HX8264E, HX8664B drivers. I'm using RGB888 interface configured via STMCubeIDE filled by resolution 800x480 with 1 layer and small buffer 320x240 located in internal SRAM on address 0x2003FFFF(i have 8MB external SDRAM but i'm trying to use small buffer in SRAM for workaround first), inverted DE polarity, clock for LTDC is 32MHz. But LCD still doesn't work. So i connected oscilloscope and i see correct 32MHz pixel clock, i see correct HSYNC but VSYNC is always low and DE sometimes sent some chaotic pulses or rest arround 1,7V. I checked connection on HW and it looks fine.

(When i try full resolution 800x480 for layer i've got transfer data error and fifo underrun error. When i tried external SDRAM which is probably badly configured im not unable to reflash STM because STLink is not able to find my STM32, then i have to full erase chip via STM32CubeProgrammer.) So i decided start wit small window buffer in internal SRAM.

 

Do you have any idea, where can be the issue?

Petr3_0-1710007166195.pngPetr3_1-1710007197328.pngPetr3_2-1710007231808.pngPetr3_3-1710007261454.png

 

    This topic has been closed for replies.
    Best answer by Petr3

    I tried to switch DE to active low and now everything is working fine. Now im going to experiment with 2 layers and external SDRAM.

    2 replies

    P
    Petr3AuthorAnswer
    Visitor II
    March 10, 2024

    I tried to switch DE to active low and now everything is working fine. Now im going to experiment with 2 layers and external SDRAM.

      K
      KDJEM.1
      Technical Moderator
      March 11, 2024

      Hello @Petr3,

      Glad to now that the issue is solved. And thank you for updating post and sharing the solution. 

      About the DE, it is mentioned in AN4861 that "Only the DE control signal must be inverted versus the DE polarity indicated in the display datasheet. The other control signals must be configured exactly like the display datasheet."

      For example if you referring to the display datasheet, and you found that HSYNC and VSYNC must be active low and the DE signal must be active high. In this case, as the DE signal is inverted in the output, it must be set to active
      low as well. The LCD_CLK signal must not be inverted.

      I recommend you to take a look to LCD-TFT display controller (LTDC) on STM32 MCUs, I think can help you to configure 2 Layers and external SDRAM.

      I hope this help you.

      Thank you for your contribution in STCommunity :).

      Kaouthar

       

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