Master Slave sync queston

[Greybeard]

I have two nucleo boards communicating over SPI.  No Interrupts; No DMA ;   Using HAL TransmitReceive(..)   Chip Select set by software.  Simple  8 char ASCII Transfer.  Everything Works....almost.  I am using a logic analyzer to monitor the interaction. 

When I start both the Master before the Slave,  every thing works.

When I start the Master After the Slave, No Data Transfer takes place.

Is this normal behavior??

How can I keep the two units in sync if the Master starts after the Slave???

Any suggestions??

[David Littell]

SPI was never intended to be a general networking technology.  To bludgeon it into submission requires (quite) a bit more coordination protocol design and implementation beyond what the HAL provides.

[Greybeard]

Thanks.  I am just getting started with SPI and trying to understand a very simple exchange between two units.  Lack of ability for the slave to sync with the master, if the master resets. is something to note and attempt to understand. 

[Andrew Neil]

There shouldn't be any problem to sync slave to master!

Chip Select marks the start & end of each transfer;

Clock clocks the bits.

 

What do you mean by, "No Data Transfer takes place" ?

Is there activity on the wires?

[mƎALLEm]

Hello,

---

When I start the Master After the Slave, No Data Transfer takes place.

---

It depends on how do you mean by "start the Master After the Slave".

The clock is generated by the master. If at that time (the master is at reset state) there is no clock seen by the slave -> no data transmitted.

[Greybeard]

Starting the master means beginning a new Debug session. Download code and running from reset

The master Pseudo Code is

Initialize stuff

While 1

    Fill the TX buffer and Zero the RX Buffer

   Reset CS

    Short wait(50us) to give the slave time to respond

   TransmitReceive(..)

   Set CS

   Long wait(1000ms)

I Thought that handling the CS should cause the two units to sync.

 

Slave pseudo code

Initialize stuff

While 1

     Fill Transmit buffer

    Zero Receive buffer

   Wait for CS to go low

        TransmitReceive(...)

   Wait for 500 ms

Code Attached