Maximum CPU Cycle for Which attempt to read the same flash memory bank stalls the bus.

[Akash Saini]

As per RM0456 Reference manual for STM32U5, any attempt to read the same flash memory bank stalls the bus. Can you please specify the maximum time/CPU clocks for which bus can be stalls.

 

Thanks,
Akash Saini

[waclawek.jan]

> Can you please specify the maximum time/CPU clocks for which bus can be stalls.

That depends on the operation on FLASH, for timing of those operations, see Flash memory characteristics chapter in datasheet.

JW