Maximum supported resolution for the STM32U5G9?

[Smith_023]

Hello, I would like to know what is the maximum display resolution that can be supported by the STM32U5G9 chip, I calculated based on the MIPI clock that I can drive a 1024x768 screen at 16 bit, but I am very unsure. Thanks for your help.

[KDJEM.1]

Hello @Smith_023 and welcome to the Community,

 

What is the display interface to be used ? DSI or LTDC ?

For LTDC interface, there is no absolute LTDC maximum resolution since it depends on several parameters such as:
• color depth
• used SDRAM bus width
• system operating speed (HCLK)
• number of AHB masters accessing concurrently to memory used for framebuffer

Please note that if DSI is used, we are limited by the 500Mbps speed per lane.

For more information, please see Section 5.2.2 Checking display compatibility considering the memory bandwidth requirements  and Section 9 Frequently asked questions in AN4861, DS14102 Section 3.41 LCD-TFT display controller (LTDC) and Section 3.42 DSI Host controller (DSI) and  AN4860 section 7.1 DSI link maximum bandwidth impact on LTDC pixel clock.

 

I hope this help you!

Thank you.

Kaouthar

[Smith_023]

Hello, KDJEM.1, thank you for your answer.

I am using a DSI display interface.

According to the STM32U5G9 user manual for DSI, the interface seems to convert LTDC to DSI, as if there is an RGB->DSI converter chip integrated within the chip, I'm not sure if I understand correctly, so I'm more interested in understanding what is the highest display resolution that this chip can drive properly with DSI?

Thank you.

[KDJEM.1]

Hello @Smith_023 ,

 

Thank you for updating post.

The maximum display resolution depends on display characteristics.

You can see on the below an example of 1024x768 display with 30Hz refresh rate calculation.

Firstly, you need to calculate the LTDC pixel clock: pixel clock = Total Width x Total Height x refresh rate = 23.59MHz.

Then, depending on the DSI color coding,  it is possible to evaluate the equivalent pixel clock as follows:
As an example, when using one data lanes at 500 Mbit/s: for 16 bits per pixel coding example maximum equivalent pixel clock is 500Mb/s / 16 bpp = 31.25 MHz
In this case the 1024x768 display with 30Hz refresh rate is supported.

Please see AN4860 

Please let me know if my reply answer your request?

Thank you.

Kaouthar

[Smith_023]

Hello, KDJEM.1

 

Thank you so much for being able to clear up my concerns.

I learned more about the DSI portion of the chip.

By the way, the STM32U5G9 is indeed a very nice chip.

 

Thank you.

[KDJEM.1]

Hi @Smith_023 ,

 

Thank you for your contribution in STCommunity and for sharing your feedback about STM32U5G9 device.

To give better visibility on the answered topics, please click on "Accept as Solution" on the reply which answered your question.

 

Thank you.

Kaouthar