maximum USART baud rate on STM32U0

[max_hai]

Hi,

I would like to determine the maximum baud rate for a USART peripheral in asynchronous mode. In the datasheet (Figure 1) the maximum baud rate is given as 8 MBit/s. But even if I set the clock for the USART peripheral (in this case USART1) to the maximum of 56 MHz (Figure 2), I'm not able to set 8 MBit/s for the baud rate. I'm able to set 7 MBit/s when I set the over-sampling to 8 samples (image3).

I'm using the Nucleo-U083 board together with the STM32CubeIDE 1.16.1.

If someone could show me how to configure the USART peripheral for 8MBit/s I would be very happy.

Kind regards Max.

image1:

 

 

 

 

image2:

Image3:

 

 

[Guenael Cadier]

Hello @max_hai 

As per my understanding, as STM32U0 max operating frequency is 56Mhz, the maximum baudrate achievable on an USART peripheral in asynchronous mode, is 56/8, so 7Mbit/s when selecting Oversampling 8 method (3.5 in Oversampling 16). So my feeling is that the information in Datasheet is not exact.

Regards

[max_hai]

Hello,

Could you please verify this information?

Because I just noticed that I can increase the USART1 clock without getting an error for that clock. But in this case I get an error for other clock domains that can only handle 56MHz, as you can see in the screenshot below. So I'm probably doing something wrong here, and a higher USART clock can be achieved with an external oscillator? But even this I cannot configure.

Regards

 

[Guenael Cadier]

@max_hai
I fowarded this remark about 8Mbits/s reference into U0 datasheets to ST U0 team. It would be corrected in next release of datasheets. The official max baudrate is 7Mbits, due to the max 56 Mhz provided to USART peripheral.

@Andrew Neil
7Mbits is also the maximum achievable in Synchronous mode.
Regards

[max_hai]

@Guenael Cadier 

Thank you for your feedback. If there is any response from the ST U0 team, please let me know as well.

Regards

[Tesla DeLorean]

Documentation lacks internal consistency

https://www.st.com/resource/en/reference_manual/rm0503-stm32u0-series-advanced-armbased-32bit-mcus-stmicroelectronics.pdf

References in one spot that the PLL Q and R taps are max 56 MHz, at the register definitions is says 54 MHz

So "5.2.9 Clock source frequency versus voltage scaling" vs "5.4.4 PLL configuration register (RCC_PLLCFGR)"

And perhaps to lesser extent assumption of AHB being 54 MHz here "21.5 RNG processing time"

 

 

An 8 Mbps USART seems a bit of a stretch