Memory Synchronization Barriers

[BDoon.1]

I am running code on an STM32U585QI that enters STOP2 when the code is idle.   I am disabling the data cache before going to stop2, and enabling it when coming out (to deal with an errata item).  My code basically does this:

HAL_DCACHE_DeInit();
HAL_PWREx_EnterSTOP2Mode();
HAL_DCACHE_Init();

 

My question is, should I tell the CM33 to synchronize before/after this as well?  Like this?

HAL_DCACHE_DeInit();
__DSB();

HAL_PWREx_EnterSTOP2Mode();
__ISB();

HAL_DCACHE_Init();

(those are cmsis_gcc.h functions to make the equivalent "dsb" and "isb" assembly calls)

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Code formatting applied - please see How to insert source code for future reference.

[EniRot99]

Yes, it is recommended to use synchronization barriers (__DSB() and __ISB()) around these operations.

Your suggested sequence is indeed appropriate:

HAL_DCACHE_DeInit();
__DSB();
HAL_PWREx_EnterSTOP2Mode();
__ISB();
HAL_DCACHE_Init();

 

__DSB() ensures that all data memory operations have completed before the processor enters STOP2 mode.
__ISB() ensures correct instruction execution context after waking from STOP2 mode, particularly after reinitializing the cache.
This approach enhances stability and reliability when transitioning in and out of STOP2 mode, particularly in systems affected by cache-related errata or sensitive timing dependencies.

[TDK]

@EniRot99 Can you provide a reference to back this up that isn't ChatGPT?

 

@BDoon.1 I suspect they are not needed, but can't find anything stating that. Including them won't hurt anything.

[EniRot99]

Based on Cortex M33 User Guide: https://documentation-service.arm.com/static/5f16e93d20b7cf4bc524af1d 

I guessed this is right, and wrote a nice Answer with ChatGPT :)