Mismatch of DTCM-RAM cache attribute in documentation

[dmocom]

In Figure 1 of the reference manual RM0433 for the STM32H743 (and STM32H742, STM32H753, STM32H750) no connection between cache and DTCM-RAM exists.

 

 

For all I know this is correct since the DTCM-RAM is not cachable.

Table 7 on the other hand shows that the DTCM is cachable.

Which one is correct? Or is my interpretation of the architecture figure wrong?

 

[STOne-32]

Dear @dmocom ,

 

Your understanding is correct for the first part , for the second part it is more about MPU attributes on the memory map and have the right policies for each MPU Region, I would recommend to read these two applications Notes : 

https://www.st.com/resource/en/application_note/an4839-level-1-cache-on-stm32f7-series-and-stm32h7-series-stmicroelectronics.pdf

 

https://www.st.com/resource/en/application_note/an4838-introduction-to-memory-protection-unit-management-on-stm32-mcus-stmicroelectronics.pdf

to have a complete overview on Level1 Cache and MPU . Hope it helps .

Cheers,

STOne-32

 

 

 

[tjaekel]

Sorry, why are you looking for a connection between DTCM and DCache?

Such one is not there (and it would not make sense):

• DTCM is "Direct Tightly Coupled Memory":
  it means: it does not need any DCache, it is the fastest memory you have, the MCU can use these DTCM memories with the same speed as the core would run
• A DTCM is never using DCache, it is also not "protected" (not covered to set Cache Policies for it) via the MPU: it is really a memory which is directly connected to the MCU (like its private and fastest memory)
• There is not any path (and no need) between DTCM and DCache: DTCM does not need to be cached - it is already directly so fast as the MCU.
  It is a dedicated interface on some ARM MCU, e.g. CM7, without any connection to something else:
  just MCU - DTCM.
• DCache is there in order to deal with memories (SRAM, Flash) which are way slower as the MCU core clock.
  They buffer data on a slow memories.
  But DTCM is the fastest memory and runs at the same speed as the MCU. No need for any DCache (and such a DTCM-Cache connection is for sure not there: not needed, not in the chip design)

Why are you looking for a DCache connection to DTCM?
(OK: there can be a cache coherency issue, e.g. doing a DMA froM DTCM vs. regular cached memories can be tricky, SW wise, to use the updated data in memory for a DMA.)

DTCM has also a dedicated memory region (base address), outside of all other regular memories. If the MCU would access this DTCM memory (via its dedicated address range) - it would newer read via a slower DCache interface (as for other memories). DTCM does not need DCache.

DTCM is the BEST you can have: any DCache interface, e.g. to regular SRAM has a lot of latency issues (e.g. Cache miss, Cache flush...). A DTCM does not have any of these "penalties" (because it does not need DCache).