Missing STM32U5 kernel clock limits

[Uwe Bonnes]

For H7, the kernel clock limit are given in Table 61 Kernel clock distribution overview as shown in

https://community.st.com/t5/stm32cubemx-mcus/stm32h745-fdcan-clock-frequency/td-p/83540

I do not find a similar table for U5 in the most recent datasheets and reference manual. If I did not look carefully enough, any hint to find it is welcome. Otherwise ST should  consider adding like for H7.

[MKANO.2]

Hello @Uwe Bonnes 

For the STM32U5, all details regarding the kernel clocks are provided in the RCC chapter and illustrated in the Clock Tree figure.

Best regards

Mariem

[Uwe Bonnes]

So please tell me where exactly to find in rm0456 RCC chapter the limits for the FDCAN kernel clock!

[MKANO.2]

When selecting pll1_q_ck as the kernel clock for FDCAN, the maximum frequency is 160 MHz , as detailed in the Datasheet’s PLL Characteristics table. This specification is also reflected in CubeMX.

[Uwe Bonnes]

We have a differing understanding of the meaning of reference manual. For me, a "reference manual" should be the reference and not some tools where with some input and click you can get some information that you can believe or not but you can not check the values against the reference manual.

[mƎALLEm]

Hello @Uwe Bonnes 

I'm asking that question internally for STM32U5. I'm getting back to you as soon I have an answer. Internal ticket number 221521.

In fact the same table is provided for STM32H5 product in the datasheet:

Thank you.