Nested interrupts on the Nucleo-F411RE

[carlosdelfino]

 

I am doing an academic activity where I was asked to execute a reading process from an external RTC via i2C, but on another MCU, I used a repeat timer, but I was unsuccessful. Something seems to interfere with the I2C communication and according to the analyzer (I am using a didactic simulator) the bus clock signal is not generated, but I see a series in the data signal exactly at the programmed time, so the firmware seems to freeze when writing to the I2C bus.

On an STM32 (especially on the Nucleo Nucleo-F411RE board) is it possible to nest the communication inside a repeat timer interrupt? I did not get to know in my studies on STM32 about which timers exist, which document should I read to learn more about this subject?

[Tesla DeLorean]

On the NVIC you can describe the "grouping" of bits describing a priority level and a preemption level, things with a lower preemption number can interrupt those other interrupt, otherwise they stack,and as you exit one IRQ Handler, it "tail-chains" into the next.

Joseph Yiu's "Essential Cortex-M3" and related book series covers this material.

With SysTick you ideally want it to preempt in HAL so the tick-count for timeouts works well. HAL call-backs occur in interrupt context, so you don't want to call blocking functions.

 

BTW you can put hyperlinks in signatures via <a href="url">describe</a>

[carlosdelfino]

I haven't yet gotten to the point in my studies on how to prioritize interrupts.

I have a lot of respect for Joseph Yiu, I have the book Definitive Guide To ARM Cortex-M23 and Cortex-M33 Processors.

I don't know if the NVIC of the Cortex-M33 is the same as that of the Cortex-M4 (stm32-f411re), but I'm going to dedicate a special reading to this section.

But if you have an example that you can give me to shorten this path, it would be of great help.

[Andrew Neil]

Note that the NVIC is an internal part of the CPU - so its operation is not specific to what board (eg, Nucleo) the chip is mounted on.

[carlosdelfino]

@guru I already understand this part related to the microcontroller structure well, but I have many doubts about the SDK and the use of registers.

[carlosdelfino]

I discovered where I was going wrong in the code and I no longer needed to adjust the interrupts, but I still have doubts about how to configure the NVIC registers to change the priority of the interrupts.

Can you give me a code example that demonstrates such an application of the NVIC registers?

[KnarfB]

for a STM32C071:

NVIC_SetPriority(SysTick_IRQn, 0); // Set highest priority
NVIC_SetPriority(TIM17_IRQHandler, 1); // Set second highest priority

The SysTick is used in HAL_Delay and many HAL functions depend on it. The above priorities ensure that the timer tick advances even while the CPU is in the periodic timer interrupt handler.

Good reads, besides the Yiu books:

A Practical guide to ARM Cortex-M Exception Handling | Interrupt

Cutting Through the Confusion with Cortex-M Interrupt Priorities - Embedded and Microcontrollers blog - Arm Community blogs - Arm Community

Cortex-M Exception Handling (Part 1) - Ivan Cibrario Bertolotti

Try feeding your questions to ChatGPT, Copilot, or a teacher. They might have more patience...

hth

KnarfB

[Dazed_N_Confused]

ChatGPT and  Copilot both will tell a lie. 

[carlosdelfino]

ChatGPT certainly helps a lot, but I've seen people do a lot of things wrong. I've been using both ChatGPT and Copilot for over a year. And I prefer to rely on the experience of a human being. Dialogue between humans is an old practice that I value a lot.

It's strange that we have a forum maintained by humans and it's suggested that we look for ChatGPT. I've tried to develop a ForumGPT myself, but the work ($$$) didn't allow it.