Nucleo-H743ZI2 SPI bus configuration

[JBeal.1]

If I want my SPI bus to have the CLOCK line high already before the active-low CHIP_SELECT (ENABLE/) line goes low, is there a way to do that?

I'm driving an AD9833 chip which requires at least 5 nsec time after CLOCK high, before ENABLE/ goes low. Looking on the scope I see this is in fact true in between words, with the clock idle high, but it is not true on the very first transfer from the Nucleo. The first transition of ENABLE/ to low happens when the clock line is also still low. Is there some SPI configuration to enable a mode of operation where the clock line is high before the ENABLE/ line first goes low?

[TDK]

You can try this:

 

And/or you can send a dummy transfer (with CS still high) to enable the peripheral before you start sending actual transfers you care about.

[tjaekel]

Consider the SPI Mode: SCLK high before nCS is asserted sounds like a need for SPI mode 3.
Check which SPI mode (0...3) you use.

SPI mode 3 should for sure set SCLK high, before nCS goes low (even the SPI bus might be floating before the transaction: a pull-up could solve).