NUCLEO-H755ZI-Q: Both CM4 and CM7 Resetting Due to WWDG (only configured to cm4)

[Ismails]

Hello,

observed that both the CM4 and CM7 cores are resetting (NUCLEO-H755ZI-Q), whereas it is expected that only the CM4 core should reset due to the Window Watchdog (WWDG2). For verification UART is configured in cm7 printing counter value. observe that after some value the counter is rested to 0, that means both cm4 and cm7 is resting, using stm32cubeide for code flash.

Best Regards 

 

 

[Sarra.S]

 

Hello @Ismails, 

the Cortex M7 is able to reset the Cortex M4 by setting up the WWDG2 and then the WWDG2 will reset the CPU2 if the WW2RSC bit in RCC_GCR is cleared.

However, this solution is not reversible, meaning the Cortex M4 cannot reset the Cortex M7 by configuring WWDG.

Are you sure about the UART configuration? have you been able to read correct counter values? 

 

[Ismails]

Hi @Sarra.S ,

Thank you for the replay

My both cores are getting reset.

Correct me if I’m wrong:

• WWDG2: Configured and initialized in CM4. I expect that if the refresh does not happen in CM4 within the configured time, then CM4 is supposed to be reset, and it should not affect the operation of CM7.

My confusion:

• Why is WWDG2 resetting my CM7 core? I know that WWDG1 is for CM7 and WWDG2 is for CM4.

Observation:

• I have my UART configured in CM7 to print an integer number incremented by one with a one-second delay. What I am observing is that the count is resetting to zero.
• Similarly, we tried in debug mode, and the reset handler is being called in CM7.

[TDK]

All watchdogs generate a system reset which resets both cores and most peripherals by pulling NRST low.

 

 

There is no watchdog that will only reset CM4. However, you could handle the EWI to do something similar.

[Ismails]

@TDK "Accepted Solution" Thank you.