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Visitor II
January 19, 2024
Solved

Octal SPI Interface

  • January 19, 2024
  • 3 replies
  • 1431 views

Hello Team,

We are considering STM32H562ZIT3QTR MCU for our design. There will be two Microcontroller in our design.

MCU consists of one Octal SPI Interface. Can other Microcontroller be interface with STM32H562ZIT3QTR through Octal SPI or we can only interface flash memory?

Regards,

Kadam

    This topic has been closed for replies.
    Best answer by KDJEM.1

    Hello @kadam ,

    For communication, the OCTOSPI can only be used as master only, it cannot be a master and slave like SPI. Please take a look to RM0481 Section 23 Octo-SPI interface (OCTOSPI).

    Note that, the  OCTOSPI interface supports the XSPI (JEDEC251ES) standard compliant feature. If the device (not only memory)  supports this standard, so, you can interface this device with OctoSPI. But, it is necessary to check the compatibility of the command between the OCTOSPI interface such as command order  (Instruction phase, Address phase, Alternate-byte phase, Dummy-cycle phase, Data phase) and the bytes number for each command.

    For MCU to MCU communication, I advise you to use SPI interface.

    Thank you.

    Kaouthar

    3 replies

    KDJEM.1Answer
    Technical Moderator
    January 19, 2024

    Hello @kadam ,

    For communication, the OCTOSPI can only be used as master only, it cannot be a master and slave like SPI. Please take a look to RM0481 Section 23 Octo-SPI interface (OCTOSPI).

    Note that, the  OCTOSPI interface supports the XSPI (JEDEC251ES) standard compliant feature. If the device (not only memory)  supports this standard, so, you can interface this device with OctoSPI. But, it is necessary to check the compatibility of the command between the OCTOSPI interface such as command order  (Instruction phase, Address phase, Alternate-byte phase, Dummy-cycle phase, Data phase) and the bytes number for each command.

    For MCU to MCU communication, I advise you to use SPI interface.

    Thank you.

    Kaouthar

    Graduate II
    January 19, 2024

    Or use a CPLD or FPGA to act as an interposed or mailbox type device between the two cores.

    Perhaps FMC and FIFO memory device(s) or Dual Port RAM?

    Technical Moderator
    January 29, 2024

    Hello @kadam ,

     

    Has your request been answered?

    If you need further clarification, please do not hesitate to share it :).

    Thank you.

    Kaouthar.