Octo/QuadSPI options for using external RAM and FLASH

[BobaJFET]

I'd like to use both external RAM and flash at the same time for an STM32H7 application. I'd like to get a better idea of what options are available for this. 

For example, 256Mbyte flash in memory mapped mode for execute in place and 4gb of SRAM indirect mode for read/write. 

Would this require two quadSPI or octoSPI ports? Or can it be done with just one port? I see in AN5050 that octoSPI supports multiplexed modes. 

Thank you. 

 

[Tesla DeLorean]

Why this approach rather than SDRAM?

How much RAM does your application need? For what purpose? Screen Frame Buffer?

Perhaps check HyperRAM  / AP Memory offerings and compatibility

Is an MCU the right choice?

[BobaJFET]

It doesn't need to be SRAM... The goal is just to expand both RAM and flash as much as possible using QSPI and OSPI. 

 

[BobaJFET]

For example, this is from AN5050. Here it's a single OSPI. I now question if this is possible with quadSPI as well, but I don't see any mention of this type of configuration in AN4760. 

 

 

[Tesla DeLorean]

I'd suggest moving very cautiously, ST keeps changing the IP, the most newly designed devices will have the most options which work most reliably, they don't go back and fix the silicon. So check the Errata and third party memory vendors functionality/compatibility guides.

@Alex - APMemory @AE_APMemory 

 

I'd advise using SDRAM as options for parts is far broader, both in foot-prints and vendors, and high volume movers.

[Alex - APMemory]

Hi,

I can only agree that checking exact STM32 device and associated supported QPSI or OPI or HPI is first things to do. 

When QSPI/OPI/HPI is supported I can only suggest to use it, rather legacy SDRAM, for pin count, power, package options and competitivness benefit. this is even more true with the Hexa interface of STM32H7S/R or STM32U599...

Below is an overview of supported device,  STM32 / IoT RAM crosslist, which may help .

 

	APMemory IoT RAM Solution
STM32 MCU family	HPI/OPI	OPI	QSPI SDR	QSPI DDR	Comment
STM32L4Rx	-	✓*	-	-	*avoid odd address write issue - ADMUX recommended
STM32L5 STM32L4P5/Q5 STM32U575/585 STM32H5	-	✓	✓	✓
STM32H7A3/B3 STM32H72x/3x	-	✓	✓*	✓	* doesn't support QSPI SDR Memory mapped Write mode
STM32U59x/U5Ax, STM32U5Fx/U5Gx STM32H7Rx/Sx	✓	✓	✓	✓
All STM32 supporting NOR QSPI	-	-	✓*	-	* doesn't support QSPI SDR Memory mapped Write mode
APMemory device	256Mb~512Mb 1.8V BGA24/WLCSP APS256XXN-OBR/OB9-... APS512XXN-OBR/OB9-...	64Mb~512Mb 1.8V ~3V BGA24/WLCSP APS6408L-xOBM-... APS12808L-xOBM-BA APS12808O-OBR-WB APS25608N-OBR-BD APS51208N-OBR-BD	16Mb~128Mb 1.8V ~3V SOP8/USON8/WLCSP APS1604M-xSQR-… APS6404L-xSQR-... APS12808O-SQRH-WA	128Mb 1.8V WLCSP APS12808O-DQ-WA
20pins, up to 1GB/s	11pins, up to 400MB/s	6pins, up to 72MB/s	7pins, up to 166MB/s

[KDJEM.1]

Hello @BobaJFET ;

 

Could you please precisely which STM32H7 device are you using?

Is the device supporting one QUADSPI interface? If you have two QUADSPI interfaces available, you can connect each memory with a different QUADSPI interface.

If you want to connect two quad memory using only QUADSPI interface, you can select a different chip select GPIO pins for each memory.

The two memories must be connected to the same QUADSPI instance. The chip select of each memory must be connected to a QUADSPI chip select GPIO. The software should configure the chip to select the GPIO pin for the memory to be accessed by driving the GPIO configuration.

I think the proposed solution2 in this FAQ may help

 

Thank you.

Kaouthar

[BobaJFET]

I have not chosen a specific H7 chip as of yet since it's dependent on this decision. I'm leaning towards using quadSPI for flash and FMC for RAM. Or, octoSPI for both RAM and flash in multiplexed mode. 

[Alex - APMemory]

Hi, 

Here are STM32H7 option for using low pin count RAM 

-STM32H7A3/B3 : Octal DDR (11pins), QSPI DDR(7pins), no QSPI SDR

-STM32H72x/3x : Octal DDR(11pins), QSPI DDR(7pins), no QSPI SDR

-STM32H7Rx/Sx : Hexa DDR(20pins), Octal DDR(11pins), QSPI DDR(7pins), QSPI SDR(6pins). With multiple Memory controller, you can separate Flash and RAM on different bus, upon pin counts

Hope this help your selection

Alex

PS: IoT RAM / SDRAM : Pin count - Performance - package (cost & package cost correlated) overview