PM0056 issues: NVIC_IPR20 offset incorrect

[ljh]

Question comes from PM0056 Programming Manual STM32F10xxx/20xxx/21xxx/L1xxxxCortex®-M3 Programming Manual Page 129

I calculated the last address is 0x350

Is it a problem with the manual?

[Tesla DeLorean]

https://electronics.stackexchange.com/questions/450897/nvic-memory-map-arm-cortex-m3-stm32f103

Yes, and the overall depth for IP[x] is not defined, it depends on specific implementation and the interrupt count in each.

@STTwo-32 

[ljh]

Don't sink my post.

[Tesla DeLorean]

Huh?

It's definitely incorrect, but been in there for years. Most would use the structure, or the ARM TRM's

Several people have been alerted to this issue.

[ljh]

Oh! It is normal to make mistakes in the manual, but it is disappointing that a problem that has existed for many years has not been corrected. Thank you for your answer.

 

[STTwo-32]

Hello @ljh and welcome to the ST Community.

Thank you so much for reporting this. I've escalated to the concerned team for correction on the coming releases (under internal ticket number 191372). Thank you @Tesla DeLorean for the mention.

Best Regards.

STTwo-32