Possible to combine two SPI flash chips into "one" larger memory?

[flyingfishfinger]

Hi,

I would like to implement a USB -> SPI flash storage solution. There are several guides and examples already available to do so (also the tinyUSB ones), so I think that should not be an issue.

However, due to physical constraints of my project, I do not have room to add one single flash chip of the requires size, but I WOULD have room for several physically smaller parts.

So, the question is this - is it possible to combine two external flash chips (either connected to the same SPI peripheral with separate CS lines, OR two separate SPI1 / SPI2 peripherals, OR to an OctoSPI interface) into "one" larger memory and access them as if they were one larger chip?

I do not have a preference of what (if any) software stack to use but I do need it to be a FAT file system in the end, I think.

Cheers,
R

[TDK]

It will depend on the chips and protocol you're using in particular. If you have parts selected, post them. If the protocol is SPI, probably not.

Generally, 1x flash chip of 2x size is going to be less of a space requirement than 2x flash chips of 1x size.

[Tesla DeLorean]

Chip level eMMC (IC equivalent to Micro SD cards) are managed NAND Flash, would be relatively ideal for File System implementations. Good for hundreds of MB, and multi GB

You can bank pairs of QSPI NOR Flash, but with a minimum 4KB Sector Erase Size, and general slowness, they are not ideal

If you bank, it interleaves, so perhaps that doubles to 8KB

[flyingfishfinger]

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@TDK wrote:

Generally, 1x flash chip of 2x size is going to be less of a space requirement than 2x flash chips of 1x size.

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 Yes, but I have a width constraint of 5mm for the entire board. I do have length, though. The ST32 chips I listed all come in WLCSP packages smaller than 4x4mm, and and the width constraint also eliminates the usual 6x8mm flash chip packages. Therefore I picked a GigaDevice GD5F4GM8 NAND, which comes in a 5x6 mm version. This is the highest capacity part I was able to find that comes in a package with at least one dimension <= 5mm, but I would like more storage - hence this question of whether I can use two.

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@Tesla DeLorean wrote:

You can bank pairs of QSPI NOR Flash, but with a minimum 4KB Sector Erase Size, and general slowness, they are not ideal

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Speed doesn't matter for my application, but I would like the maximum possible capacity. How would banking work here? Switch when one is full?

And sadly eMMC chips don't fit my width constraint mentioned above, I already looked into that :\

R

[Tesla DeLorean]

 >>Switch when one is full?

For NAND like this, I'd use multiple chip selects, and divide down the BLOCK address space among the chips.

ie first 512MB (4Gb) in the first chip, second 512MB in the second, etc.

[flyingfishfinger]

Ok, that makes sense. So that means the maximum wasted space per chip is < 1 block size, right? I also assume you mean to connect them to the same SPI(x) peripheral with separate CS instead of using the second peripheral.

Once I get MSC working with one chip, would you be able to give me some tips on implementing this? 

I'm not a software person by any means, so I'll be prodding my way through by the examples. I will probably use TinyUSB with a Nucleo-NUCLEO-C071RB, since it comes with a flash-based dual-LUN example and a way to use it in the STM32CubeIDE without a RTOS.