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Graduate
January 10, 2025
Question

PVD on STM32L4 with external input

  • January 10, 2025
  • 4 replies
  • 825 views

Hi

On STM32L4xx Ref Man 

Programmable voltage detector (PVD) supports external input PVD_IN.

How to configure the GPIO for PVD_IN (ex STM32L4 PB7)?

How to configure VREFINT?

Is there any example?

    This topic has been closed for replies.

    4 replies

    ST Employee
    January 10, 2025

    Hello @CanRF 

    As an example on STM32L476 device (Nucleo-L476RG)

    According to DS10198 Rev 11 in Table 16. PVD_IN is an additional function connected to PB7. 
    And in RM0351 Rev10, PVD can be configured in PWR_CR2 bits PLS[2:0] = 111.

    In STM32CubeMX here the possible PVD levels configurations:

    RomainR_0-1736524842484.png

    The internal voltage reference VREFINT is calibrated in production with VDDA=VREF=3.0V at 30°C, is around 1.2V (see DS10198 Table 26) and it is enabled when VDDA and VSSA are supplied.

    Best regards,

    Romain,

    CanRFAuthor
    Graduate
    January 13, 2025

    Hi Romain

    Thanks for your information.

    DS10198 Rev 11 and RM0351 i read before. But I didn't see information for the GPIO configuration nor the VRefint configuration.

    From MX Cube I see, that PB7 is configured as analog with no pullup/down.

    This was also my intention but i didn't find it in the docs.

    Where did you get the information, that VRefint is available when VDDA and VSSA are supplied?

    For ADC conversion of VRefInt VREFEN of ADCx_CCR must be enabled.

    Can PVD use VRefInt Independent of ADC and VREFEN?

    Thanks for clarification

    Best regards, 

    RF

    ST Employee
    January 13, 2025

    Hi @CanRF 

    Sorry, I made a mistake and I misled you. I mixed up the VREFINT bandgap with the VREFBUF.

    I'm referring to RM0351 in section 5 Power control (PWR)

    • VREFINT is powered by VDD (not VDDA) and is related to Power management (PMU) 

    RomainR_0-1736784589228.png

    • The VREFEN control bit is specific to ADC input for internal conversion.

    RomainR_1-1736785635108.png

    RomainR_2-1736785704337.png

    When PLS[2:0] = 0b111 in PWR_CR2 register. The external input analog voltage PVD_IN is compared internally to VREFINT. It's independent from ADC.

    Best regards,

    Romain,

    CanRFAuthor
    Graduate
    January 21, 2025

    Hi Romain

    Again thanks for your information.

    This helps a lot,

    But now I've an additional problem.

    On startup I want to wait until the power is over the selected voltage.

    So I configure PVD and wait until PDVO is 0.

     I use the following code

    ...

        HAL_PWR_ConfigPVD(&sInit);

        LL_PWR_EnablePVD( );

        while(0U != LL_PWR_IsActiveFlag_PVDO( ))
        {
        }
    ...
     
    But PVDO is always 0 after PVDE is set.
    I think the PVD need some time to startup.
    I test a delay between LL_PWR_EnablePVD( ); and LL_PWR_IsActiveFlag_PVDO( ).
    With about 160us PVDO has the correct value.
    Is this time and behavior anywhere documented.
     
    Thanks for clarification.
    RF