PWM dithering for noise mitigation

[Rob1]

Hi to all.

I have an H-bridge motor drive that I'm having some EMC issues with. There are always conflicting requirements. I want to drive the FET's hard , for power dissipation reasons , but faster gate rise times mean higher harmonic frequency generation. Would PWM dithering help in this regard. It's something that is used a lot in SMPS controller chips to reduce noise , so I assume it could also be used in a PWM drive circuit.

I realize that PCB layout is probably the biggest influencing factor in EMC/EMI issues , but everything I can add to reduce noise will help. I'm limited to a 2 layer board , so layout is tricky.

Cheers

Rob

[MasterT]

I don't see stm32F4 Timers support dithering in hardware, so there are 2 options:

1. dithering in software, 

2. acivate PLL spread spectrum clock generation (SSCG).

[tjaekel]

For my five cents: you mix up "dithering" with "slew rate":

Dithering, as I know (from audio) is: randomize the lowest bits (with a real random noise).
If you would do on a PWM audio signal: it looks like just the PWM signal is a bit more jittering.

But it does not change the "Slew Rate": all the digital signals come with the same "transition speed" still, so the edges of the digital signal is not affected by dithering.

The digital signal edges generate all the EMI effects (the very high frequency noise due to very fast rectangle signal transitions/edges).

You could play with the "Slew Rate" (in STM32 MCU often the Speed settings, Drive Strength). But it might not help really:

If you lower the Drive Strength, the Slew Rate - OK, the edges are not so "sharp" anymore, more like a "ramp": this reduces the EMI effects (the very high harmonics coming from these sharp edges).
But: if your FET driver (where you send the signals to), has a "threshold" and "hysteresis" (in order to decide if input signal was low or high) - it will still generate very fast digital edges on the power output side.
If it is a "digital switch", even you increase the Slew Rate on input signal - it will still switch very fast from one state to the other.

I assume, all your issues come after the FET driver (power switch): this EMI travels along the power rails and supply. There is nothing you can do with dithering on the MCU side (still very sharp edges everywhere).

You might need to design a power supply circuit, structure, which "eliminates" the EMI and power ripples spread via the power distribution.
My hints:
the power after the FET drives must be very low impedance. A lot of margin to deal with current peaks.
Keep MCU and FET Output power separate, at best: from different power sources.
Avoid "cross talk" by routing two different power rails to long in parallel on PCB.
Separate "analog and digital" domain, here: separate MCU Power Domain from Out Power Domain.
Route all signals with very GND return path (even GND should not "share" same path).

Digital logic creates always harmonics (and EMI). Just a slower "edge transition" (Slew Rate) helps a bit. Dithering, on digital bits, will not improve anything in terms of "harmonics": instead: adding "random noise" on LSB bits can make it even worth (now you have even faster changing bit combinations and even more EMI noise).

[Rob1]

I'm not mixing up dithering and slew rate. I want a high slew rate to improve ( reduce) the power loss.

High slew rate however results in higher harmonics and hence EMI/EMC issues.

I want to dither the PWM to spread the harmonic frequencies over a wider bandwidth. This should reduce the

amplitude that is detected by the quasi-peak detector in the EMC lab. Basically the energy is "spread" over

a wider bandwidth , so is lower in amplitude. 

Rob