QSPI Slave mode? PSSI in 2bit-packing mode? There must be a way...

[BarryWhit]

I have an application which requires me to send unidirectional high-speed parallel data on preferably 2 (or 4) from several synchronous sources to an STM32. I'm thinking of using the U575, but that's not set in stone.

My requirements do not seem to fit any of the canned peripherals, thought several come so very close:

1. I'd like to use as few pins as possible (so using 8bit PSSI is out, and this would waste a lot of SRAM if DMA us used to store 2 bits per 8 bits of memory)

2. The clock is generated externally to the STM32 (AFAICT, this rules out OctoSPI in dual mode, since it is designed to be a master, and seems tailored to memory access)

3. I'd like the design to be minimal/simple (which means I'd like to avoid using one SPI periph per lane, and sharing the clock. Though this currently looks like the only workable way).

4. The clock is somewhere above 10Mhz, so using GPIO and EXTI seems unlikely to work.

5. There is limited processing done on the data. It's more of a capture/analyze type of scenario.

 

Ideally, I would like to be able to use something like 2 PSSI pins only (its handshake signals are a bonus), and have the "fantasy" feature of a configurable way to pack the incoming bits memory, with DMA.

Alternatively, I'd be happy with QSPI in dual mode (since it also has FIFOs, the missing handshake signals aren't a deal-breaker, and even without packing flexibility, I can always unpack during data processing), if only it would accept an external clock.

 

Is there any way to do this with existing peripherals?

 

Your help and advice much appreciated,

 

 

[Tesla DeLorean]

DCMI has some tolerance for different clocking, up to 54 MHz and unrelated to the MCU, as I recall

ST missed the boat on DRQ/DACK type DMA, although TIM CHx input triggering of GPIO to Memory, or FMC to Memory could be done.

You can use FIFO memories

FMC to FPGA would give you the most flexibility

 

[BarryWhit]

Thanks. It's not DCMI, though.

 

CPLD->PSSI was the alternative I had in mind, but It'd be better to save the extra 5-10$ part.

 

I could use a FIFO or shift registers, but If  I'm adding something to the BOM I might as well add a CPLD and "nuke it from space".

 

Recent offerings from ST suggest that internally they're quite fond of this "DMA packing" feature. If only they included such functionality in the PSSI. We'd get all the benefits (handshake signals, High throughput), without assigning more pins than needed, or being handcuffed to a bus width.

 

> ST missed the boat on DRQ/DACK type DMA, although TIM CHx input triggering of GPIO to Memory, or FMC to Memory could be done.

PSSI does have something close to that.

You mean sommthing like Input-Capture->DMA/Interrupt(GPIO->Mem)?

From what I've read this is limited to 8-10Mhz at most. PSSI can go about as fast as the bus allows (and supports packing to optimize bus access, at that)

[Tesla DeLorean]

TIM+DMA+GPIO speed depends on the MCU, I could swear it was 21 MHz on some of the F4's, some others it was much slower, like the H7 due to being several buses away. Also limited to 16-bits on a common GPIO Bank

PSSI seems to have been invented to push it back more into the hardware domain and however more buffered/efficient they can make that rather than saturate the processor buses. And deal with the slowness they'd caused in the current implementation of the GPIO fabric.

The AVERLOGIC AL422B type FIFO memories allow for asymmetry in acquisition rate, and burst consumption. Would be good for Logic Analyzer type application. Something that could be mapped to the FMC

[BarryWhit]

Sorry if this is a silly question, but isn't FMC oriented towards address based busses? how do you adapt it for a "push" type of transfer idiom (no address, latch data on clock edge)?  

 

> PSSI seems to have been invented

PSSI is actually perfect for what I need, but to utilize it properly I'm forced to put n x (parallel-out shift register) in front of it, since they haven't made the bus-width flexible.

 

> The AVERLOGIC AL422B type FIFO memories allow for asymmetry in acquisition rate, and burst consumption.

> Would be good for Logic Analyzer type application. Something that could be mapped to the FMC

Looks perfect, but appears to be made of purest unobtanium, and probably not that big a price difference from the smallest EPM240 even if I could locate stock.

[Tesla DeLorean]

The FMC can utilize as many or as few address/data pins as one wants to use. A NAND Flash typically uses only a few to address different registers in the command and data space on a device that can span 100's of GB, one typically uses a Higher Order Address Bit, so you can "memcpy" into a data buffer / FIFO type construct. You can't actually access as Linear Memory.

The FMC brings to the table a method to map a peripheral, state-machine, memory, or whatever into the ARM's physical address space. DMA can operate within this address space, the MCU, or the debugger.

 

The AL422B was cites as a Class of Device that at one point existed and might be available in other forms be it from secondary sources, clones, equivalent, etc. Cited as a COTS type solution, yes could probably manifested from a moderately priced CPLD / FPGA as sizes and costs shrink.

[BarryWhit]

> The AL422B was cites as a Class of Devices

sure, but I was mostly intrigued by your mention that it can do packing which seems exotic for FIFO chips (you can still find those, certainly).

 

> The FMC brings to the table a method to map a peripheral, state-machine, memory, or whatever into the ARM's physical address space. DMA can operate within this address space, the MCU, or the debugger.

Yes, but that still means the MCU initiates access, instead of "absorbing" data pushed by the external sources, which is a requirement. Can it be used that way? My pokes and prods at CubeMX suggest not.

 

And even if you can leave as many address/data lines as you want unconnected, doesn't that mean the peripheral still takes them over so they can't be used for other things? Can you reconfigure pins claimed by a peripheral to another AF without issue, if they are unused? And even if you could reassign those pins, if you're using 2/8 data pins only. then DMA from the FMC will waste 6 bits (80%) per sram byte (a scarce resource).... There's all sorts of hiccups with this approach.