Solved
Question when setting up the ETH Receive Descriptor Tail pointer
Hello there!
I'm reading the STM32H5 documentation on how to setup the ETH descriptors correctly. At the same time I'm following the HAL for the same H5 series.
When the RX descriptors are initialized, I can see the HAL assumes there are 4 descriptors.
/* Set Receive Descriptor Ring Length */
WRITE_REG(heth->Instance->DMACRDRLR, ((uint32_t)(ETH_RX_DESC_CNT - 1U)));
/* Set Receive Descriptor List Address */
WRITE_REG(heth->Instance->DMACRDLAR, (uint32_t) heth->Init.RxDesc);
/* Set Receive Descriptor Tail pointer Address */
WRITE_REG(heth->Instance->DMACRDTPR, ((uint32_t) &heth->Init.RxDesc[ETH_RX_DESC_CNT - 1]));
ETH_RX_DESC_CNT is 4 and so, the ring length is 3. Correct.
The DMACRDLAR is also pointing to the correct start. I've created 4 ETH_DMADescTypeDef:
static ETH_DMADescTypeDef dma_rx_dscr_tab[ETH_RX_DESC_CNT];
Which I then point it to the respective ETH handle:
/* Provides the address of the first DMA Rx descriptor in the list */
heth.Init.RxDesc = dma_rx_dscr_tab;
All good until now.
My question is regarding the address of the tail pointer.
My question is regarding the address of the tail pointer.
WRITE_REG(heth->Instance->DMACRDTPR, ((uint32_t)(heth->Init.RxDesc + (uint32_t)(ETH_RX_DESC_CNT - 1U))));
Due to the size of ETH_DMADescTypeDef, wouldn't the address of DMACRDTPR turn out to be completely wrong?
I would assume it should be something like this:
WRITE_REG(heth->Instance->DMACRDTPR, ((uint32_t) &heth->Init.RxDesc[ETH_RX_DESC_CNT - 1]));
Let me know what you think!