Hello @Nitin,
I made a check on my side.
First, there is a small error in region_defs.h:
Line 213 and also line 220
Please replace
#ifdef SRAM3_BASE
by
#ifdef _SRAM3_BASE_NS
The SRAM3_BASE is actually not known when using gcc preprocessor on linker file.
After that you need to make duplicate and adapt this unsecure_sram1 function like this:
static void unsecure_sram3(uint32_t start, uint32_t end)
{
MPCBB_ConfigTypeDef MPCBB_desc;
uint32_t regwrite = 0xffffffff;
uint32_t index;
uint32_t block_start = (start - SRAM3_BASE) / GTZC_MPCBB_BLOCK_SIZE;
uint32_t block_end = block_start + ((end - start) + 1) / GTZC_MPCBB_BLOCK_SIZE;
if (start & 0xff)
/* Check alignment to avoid further problem */
/* FIX ME */
while (1);
if (HAL_GTZC_MPCBB_GetConfigMem(SRAM3_BASE, &MPCBB_desc) != HAL_OK)
{
/* FIX ME */
Error_Handler();
}
for (index = 0; index < SRAM3_SIZE / GTZC_MPCBB_BLOCK_SIZE; index++)
{
/* clean register on index aligned */
if (!(index & 0x1f))
{
regwrite = 0xffffffff;
}
if ((index >= block_start) && (index < block_end))
{
regwrite = regwrite & ~(1 << (index & 0x1f));
}
/* write register when 32 sub block are set */
if ((index & 0x1f) == 0x1f)
{
MPCBB_desc.AttributeConfig.MPCBB_SecConfig_array[index >> 5] = regwrite;
}
}
if (HAL_GTZC_MPCBB_ConfigMem(SRAM3_BASE, &MPCBB_desc) != HAL_OK)
/* FIX ME */
{
Error_Handler();
}
}
Then add the call in MX_GTZC_Init
static void MX_GTZC_Init(void)
{
if (HAL_GTZC_TZSC_ConfigPeriphAttributes(GTZC_PERIPH_ICACHE_REG,
GTZC_TZSC_PERIPH_SEC | GTZC_TZSC_PERIPH_NPRIV) != HAL_OK)
{
Error_Handler();
}
unsecure_sram1(NS_DATA_START, NS_DATA_LIMIT);
unsecure_sram3(NS_DATA_START_2, NS_DATA_LIMIT_2);
}
Finally, in linker file replace
RAM (xrw) : ORIGIN = NS_DATA_START, LENGTH = NS_DATA_SIZE
by
RAM (xrw) : ORIGIN = NS_DATA_START_2, LENGTH = NS_DATA_SIZE_2
So, with these changes you can use SRAM3 instead of SRAM1.
Best regards
Jocelyn