RM0456 discrepancy in ADC oversampling right shift

[nicolas]

In the RM0456 at 33.4.31 Oversampler it say:

The division coefficient M consists of a right bit shift up to 10 bits, and is defined using the OVSS[3:0] bits in the ADC_CFGR2 register.

But at 33.6.5 ADC configuration register 2 (ADC_CFGR2), it allow up to 11 bits:

Bits 8:5 OVSS[3:0]: Oversampling right shift
1011: 11-bit right shift

[mƎALLEm]

Hello @nicolas,

I will ask internally what's the correct the oversampling right shift available and fix the document accordingly.

Thank you for your contribution. Internal ticket 221624.

[mƎALLEm]

Sorry I need to unmark the solution until an answer is provided :)

 

[mƎALLEm]

Hello @nicolas ,

OVSS[3:0] supports up to 15 bit. Therefore, limit to 10 bit and reserved values in bitfield description will be removed. in RM0456.