RS485 non standard data word

[tasifacij]

Hi,

uc: stm32f446

 

I have a question regarding non standard word length over RS485.

I need to receive next frame over RS485

1 start bit, 16-bit data word, 2 stop bits, in total 19 bits.

UART implementation allows to receive 8 or 9-bit data words.

Could you please advice what can be an approcach to achieve?

 

Best regards, Taras.

 

[waclawek.jan]

You can't receive this using the native UART in 'F4, so you need to resort to bit-banging, possibly using timer interrupts.

JW

[Andrew Neil]

As @waclawek.jan said, you're going to have to bit-bang this.

You might start by looking at AN4457, Implementing an emulated UART on STM32F4 microcontrollers:

https://www.st.com/resource/en/application_note/an4457-implementing-an-emulated-uart-on-stm32f4-microcontrollers-stmicroelectronics.pdf

and adjust its number of data bits.

 

It might be possible to synthesise something using the SPI peripheral, but it would rely on being able to accurately control the timing between 2 transfers ...

EDIT: the QSPI can do 32-bit transfers ...

 

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@tasifacij wrote:

I need to receive next frame over RS485

---

Presumably, this is determined by some 3rd-party equipment you're having to communicate with?

Have you tried contacting the manufacturer of that equipment - do they have any suggestions?

Have you tried searching to see how others have communicated with that thing?

[tasifacij]

>>>Presumably, this is determined by some 3rd-party equipment you're having to communicate with?

>>>Have you tried contacting the manufacturer of that equipment - do they have any suggestions?

You are quite right, this is 3rd party with proprietary proto. 

 

>>>Have you tried searching to see how others have communicated with that thing?

Not much luck.

I will try your suggestion. I appreciate the answer.

[Andrew Neil]

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@tasifacij wrote:

this is 3rd party with proprietary proto. 

---

Can you give us a name? Or other details?

Maybe someone here has done it, or heard of it ...

[tasifacij]

Hi, @Andrew Neil , @waclawek.jan ,

appreciate your suggestions, they pushed me toward the solution.

Actually, I  solved the problem with IC( falling + rising edges ) + DMA. DMA catches CCR2.

ClockFreq=84Mhz

BitRate=2.73Nhz

X = ClockFreq / BitRate gives me [ticks/bit]

 

And I see the difference in clock ticks between every falling  and rising edge.

where c0 - first falling edge, stop bit started

c1 - rising edge, c2 falling edge

(c2 - c1) / X  gives me the number of bits I can set equal to 1.

And of course (c1 - c0) + ( c2 - c1 ) is length of the parcel.

[zhaowhong]

There is something wrong with your system architecture. The real product does not do this. You should add a 485 chip connected to the UATR of the CPU.

[Andrew Neil]

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@zhaowhong wrote:

 The real product does not do this. .

---

So what does it do ?

Do you have a link?

[waclawek.jan]

There may be some asymmetry in measured duration of "high" and "low" level due to the edges not being perfectly sharp and the decision level not being exactly at the middle of the edge.

Is that a fatal problem in decoding? Post some concrete values.

JW

[tasifacij]

I had a uart with non-standard word length( 16 bits ). This is all it does.

[Andrew Neil]

Sorry, it was @zhaowhong who said,  "The real product does not do this"

 

But can't you give any more detail of what you do have than just, "Fanuc encoder"?

A part number? A link to a datasheet or Product Page? Anything??