Setting the F407 FSMC WaitSignalPolarity default value

[Toneski]

Hi All,

I have a 407 connected to an FPGA using the FSMC interface.

When I compile my device configuration from ST Cube, the WaitSignalPolarity value in the MX_FSMC_Init routine is always set to: FSMC_WAIT_SIGNAL_POLARITY_LOW. On my system I need this setting to be FSMC_WAIT_SIGNAL_POLARITY_HIGH, but cannot find a way of setting this value through CubeMX.

Has anyone else found this issue or know how to fix it? Its getting a real pain having to manually update the source code before recompiling.

Kind Regards,

Tony

[FBL]

Hello @Toneski 

 

Could you please share a screenshot of the FMC peripheral registers?

 

[Toneski]

Hi,

How do you mean a screen shot? As a capture from within a debug session or a configuration settings view.

In case you need how the FSMC is setup, I attach the code that I use for configuration:-

hsram1.Init.NSBank = FSMC_NORSRAM_BANK1;

hsram1.Init.DataAddressMux = FSMC_DATA_ADDRESS_MUX_ENABLE;

hsram1.Init.MemoryType = FSMC_MEMORY_TYPE_PSRAM;

hsram1.Init.MemoryDataWidth = FSMC_NORSRAM_MEM_BUS_WIDTH_16;

hsram1.Init.BurstAccessMode = FSMC_BURST_ACCESS_MODE_ENABLE;

hsram1.Init.WaitSignalPolarity = FSMC_WAIT_SIGNAL_POLARITY_HIGH;

hsram1.Init.WrapMode = FSMC_WRAP_MODE_DISABLE;

hsram1.Init.WaitSignalActive = FSMC_WAIT_TIMING_BEFORE_WS;

hsram1.Init.WriteOperation = FSMC_WRITE_OPERATION_ENABLE;

hsram1.Init.WaitSignal = FSMC_WAIT_SIGNAL_DISABLE;

hsram1.Init.ExtendedMode = FSMC_EXTENDED_MODE_DISABLE;

hsram1.Init.AsynchronousWait = FSMC_ASYNCHRONOUS_WAIT_DISABLE;

hsram1.Init.WriteBurst = FSMC_WRITE_BURST_ENABLE;

hsram1.Init.PageSize = FSMC_PAGE_SIZE_NONE;

 

This is how I need the FSMC setup. After re-compiling the code from the IDE, I get exactly the same, but with:-

hsram1.Init.WaitSignalPolarity = FSMC_WAIT_SIGNAL_POLARITY_LOW;

Set.

 

Applogies for the delay in replying - I've only just noticed.

Regards,

 

 

 

[FBL]

Yess @Toneski . This would be helpful to follow up on this case.

 

[Toneski]

Hi F.Belaid,

Please find attached a register dump of the FSMC as setup for my project.

Hope this helps.

Regards, Toneski.

[Toneski]

...Another copy, but with BCR1 expanded.

 

[FBL]

Hello @Toneski 

 

Could you check that the memory being used, actually, our controller does not support cross boundary page for Cellular RAM 1.5.

Also, using multiplexed IOs PSRAM, could you please check the address bus A[25,16].

[Toneski]

Hi @FBL,

I am not using memory through the FSMC (well - none that is directly usable as memory for the CPU) - as per the initial post, I am accessing an FPGA through the FSMC. 

Everything I need can be accessed through a 64K page, so I haven't investigated A[25:16] - as long as the FSMC triggers the external chip select when accessing 0x6000xxxx I'm happy.

Everything works fine, except that the WaitSignalPolarity value in the MX_FSMC_Init routine is always set to: FSMC_WAIT_SIGNAL_POLARITY_LOW. 

Would it be possible to have this setting to be FSMC_WAIT_SIGNAL_POLARITY_HIGH - I cannot find a way of setting this value through CubeMX.

Does this help at all?

Regards,

Toneski

[FBL]

Hello again @Toneski 

Could you please share your IOC file? For instance, you can force it in user defined code. It should not get changed after regenerating the code.

 

 /* USER CODE BEGIN FSMC_Init 2 */
 hsram1.Init.WaitSignalPolarity = FSMC_WAIT_SIGNAL_POLARITY_HIGH;

 if (HAL_SRAM_Init(&hsram1, &Timing, NULL) != HAL_OK)
 {
 Error_Handler( );
 }
 /* USER CODE END FSMC_Init 2 */

 

Which CubeIDE version do you use?

[Toneski]

Further info - I reconfigure the FSMC_BTR1 reg soon after the FSMC is setup. Do you think I should re-configure the Wait signal polarity here too?

// Correct configuration for FSMC BTR1 register.. (Appologies for the incorrect tabulation - your website screws it all up...

FSMC_BTR1 = (0 << 24) | // DATLAT

(5 << 20) | // CLKDIV - 1 doesn't work on the prototype, 5 defo works, but is slow - need to PCB this

// Gives 168Mhz/(5+1) for io clock :- 28Mhz, so 4 clocks for 16 bit word

// 5 clocks for 32 bit!!

// 7 MegAccesses for 16 bit = 14MB/s, 8.4MegAccesses for 32 bit = 22.4MB/s

(0 << 16) | // BUSTURN

(2 << 8 ) | // DATAST - No care for synchronous accesses

(15 << 4 ) | // ADDHLD - No care for synchronous

(15 << 0 ); // ADDSET - No care for PSRAM accesses

Regards,

Toneski

[Toneski]

Hi @FBL,

I thought about setting it within a USER CODE segment, but there isn't one between the value getting set and the call to HAL_SRAM_Init as shown here...

 

hsram1.Init.BurstAccessMode = FSMC_BURST_ACCESS_MODE_ENABLE;

hsram1.Init.WaitSignalPolarity = FSMC_WAIT_SIGNAL_POLARITY_HIGH;

hsram1.Init.WrapMode = FSMC_WRAP_MODE_DISABLE;

hsram1.Init.WaitSignalActive = FSMC_WAIT_TIMING_BEFORE_WS;

hsram1.Init.WriteOperation = FSMC_WRITE_OPERATION_ENABLE;

hsram1.Init.WaitSignal = FSMC_WAIT_SIGNAL_DISABLE;

hsram1.Init.ExtendedMode = FSMC_EXTENDED_MODE_DISABLE;

hsram1.Init.AsynchronousWait = FSMC_ASYNCHRONOUS_WAIT_DISABLE;

hsram1.Init.WriteBurst = FSMC_WRITE_BURST_ENABLE;

hsram1.Init.PageSize = FSMC_PAGE_SIZE_NONE;

/* Timing */

Timing.AddressSetupTime = 15;

Timing.AddressHoldTime = 15;

Timing.DataSetupTime = 255;

Timing.BusTurnAroundDuration = 0;

Timing.CLKDivision = 4;

Timing.DataLatency = 2;

Timing.AccessMode = FSMC_ACCESS_MODE_A;

/* ExtTiming */

 

if (HAL_SRAM_Init(&hsram1, &Timing, NULL) != HAL_OK)

{

Error_Handler( );

}

/* USER CODE BEGIN FSMC_Init 2 */

 

I am using CubeIDE Version: 1.13.1 - Build: 17479_20230728_0839 (UTC)

I've attached my IOC file...

Regards,

Toneski.

[FBL]

An internal ticket 167494 has been submitted to update the SVD file to include all BCR bit fields in STM32F4 SVD file and update FMC BCR register.