Some STM32 do not like JTAG debugging
Beside my Nucleo-H7S3L8 board, I have other boards where the MCU can do JTAG and have JTAG pin accessible, but neither STM32CubeProgrammer not OpenOCD and other programmers can detect/attach via JTAG. SWD works works fine on these boards
Here the output of the Log window of STM32CubeProgrammer of two similar boards with STM32L412KB chips with full JTAG connections, NJRST pin is left unconnected. First I connected the jtag-detectable board, than the undetectable:
15:44:20 : STM32CubeProgrammer API v2.16.0 | Linux-64Bits
15:44:26 : UR connection mode is defined with the HWrst reset mode
15:44:26 : ST-LINK SN : 51FF6D064888524933312587
15:44:26 : ST-LINK FW : V2J43S7
15:44:26 : Board : --
15:44:26 : Voltage : 3,24V
15:44:26 : JTAG freq : 9000 KHz
15:44:26 : Connect mode: Under Reset
15:44:26 : Reset mode : Hardware reset
15:44:26 : Device ID : 0x464
15:44:26 : Revision ID : Rev A
15:44:26 : Debug in Low Power mode enabled.
15:44:26 : UPLOADING OPTION BYTES DATA ...
15:44:26 : Bank : 0x00
15:44:26 : Address : 0x40022020
15:44:26 : Size : 20 Bytes
15:44:26 : UPLOADING ...
15:44:26 : Size : 1024 Bytes
15:44:26 : Address : 0x8000000
15:44:26 : Read progress:
15:44:26 : Data read successfully
15:44:26 : Time elapsed during the read operation is: 00:00:00.006
15:44:43 : Error: Unable to get core ID
15:44:43 : Error: Unable to get core ID
15:44:43 : Error: Unable to get core ID
15:44:43 : Warning: Connection to device 0x464 is lost
15:44:44 : Disconnected from device.
--- Connect to other board!
15:44:55 : UR connection mode is defined with the HWrst reset mode
15:44:55 : ST-LINK SN : 51FF6D064888524933312587
15:44:55 : ST-LINK FW : V2J43S7
15:44:55 : Board : --
15:44:55 : Voltage : 3,26V
15:44:55 : ST-LINK error (DEV_UNKNOWN_MCU_TARGET)
15:44:55 : ST-LINK SN : 51FF6D064888524933312587
15:44:55 : ST-LINK FW : V2J43S7
15:44:55 : Board : --
15:44:55 : Voltage : 3,26V
15:44:55 : Error: ST-LINK error (DEV_UNKNOWN_MCU_TARGET)
On both boards, e.g. openocd with a low level debugger can detect the chain via JTAG, but the undetectable board on the next access to a DP register all high bits are returned, also for the ACK bits.
