SPI as master and FPGA as slave for some bits

[SMusc.1]

Hello everybody. I asking now for some help on my new project. On my stm32 u575zit-q i want send some bits, as master, on the FPGA EP2C5T144C8N as slave. This FPGA board is very simple (have no other peripherals on it). So i want send by means SPI, four bits in one pin of the FPGA. I know how write code for the SPI in stm32 using MOSI, CS, but now i am focused on SCK (serial clock) that the FPGA need to use for read some bit. I tried to found some on the web but i didnt. Have some one things to help me? On CUBE IDE i see the baude rate (Mbits/s for example set to 1 Mbit/s), but what aboout the SCK that the stm32 board transmit on the SPI pin? I have one idea of how i can implement and i share this with you: on CUBE IDE, if i knew the sck frequency, then i can set some check on my FPGA for read on the rising edge of the sck line, the data sending on the MOSI line of the STM32 board and load this value in some interna register of my FPGA to use it as I need later.

 

I hope that my issue is clear and say thank to all in advance.

[Andrew Neil]

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@SMusc.1 wrote:

 I know how write code for the SPI in stm32 using MOSI, CS, but now i am focused on SCK (serial clock) that the FPGA need .

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The SCK clock is essential to any SPI operation - you can't have SPI without SCK - so it's not clear what you mean by this?

You cannot have SPI with just MOSI and CS.

https://en.wikipedia.org/wiki/Serial_Peripheral_Interface

The whole SPI interface - MOSI, MISO, and SCK - is managed by the STM32's SPI hardware (with CS, you have the option of doing it in hardware or software)

https://wiki.st.com/stm32mcu/wiki/Getting_started_with_SPI 

 

See the Datasheet and Reference Manual for your specific chip for full details.

https://www.st.com/en/microcontrollers-microprocessors/stm32u575zi.html#documentation

The examples in STM32CubeMX (whether standalone or integrated in the CubeIDE) include SPI.

 

PS:

Application Note AN5543 Guidelines for enhanced SPI communication on STM32 MCUs and MPUs:

https://www.st.com/resource/en/application_note/an5543-guidelines-for-enhanced-spi-communication-on-stm32-mcus-and-mpus-stmicroelectronics.pdf

[SMusc.1]

Hi Andrew, it know that SCK is essential but as i know, the sck is a frequency that need to read some value on the varius setting mode (SPI Mode 0 for example), so every rising edge of the sck the slave read the data line of the MOSI. Question: the sck is auto set by selecting SPI setting (this my doubt) or i need to set some timer on some pin as sck? Since i am using stm32 board as master and FPGA board as slave, i think i need to know the sck to say to FPGA when read the data on MOSI line.  

[mƎALLEm]

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@SMusc.1 wrote:

 Question: the sck is auto set by selecting SPI setting (this my doubt) or i need to set some timer on some pin as sck? .  

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SCK clock is generated by the SPI peripheral itself in master mode. No need to take care of its generation!

[mƎALLEm]

Hello,

What do you mean by this? the maximum clock frequency that the SPI can generate?

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@SMusc.1 wrote:

but what aboout the SCK that the stm32 board transmit on the SPI pin? 

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But you need also to know the maximum frequency that your FPGA can sustain as SPI clock.