SPI CLK frequency dividing method

[pass3master]

SPI CLK frequency dividing method

In microcontroller (STM32H43), SPI1, 2, and 3 use a common CLK Source.
Is it possible to separate these CLK Sources?

Also, I would like to divide SPI2 and 3 more than 256 divisions, but is that possible?
Please help me.

[SabTuna]

 

The STM32H43 microcontroller utilizes a shared clock source (CLK) for SPI1, SPI2, and SPI3. It's not feasible to isolate the clock source for these SPI modules as they rely on the same PLL or system clock.

Concerning SPI clock frequency division, the maximum divider factor for SPI modules is 256. Consequently, a division factor exceeding 256 is not directly achievable for SPI2 and SPI3. To attain a lower frequency, you might need to adjust the main clock source used by SPI to a lower frequency or employ an external component for additional division.

English not my first language I write this with some AI.